82870P2P64H2 Datasheet, PDF (157/217 Pages) –

Functional Description
R
4.5.3
Hub Interface Fence Special Cycle
When the P64H2 performs a memory write transaction from one PCI bus to its peer PCI bus, the
MCH component needs to be notified. This is because the MCH has separate pipes for requests
originating on each bus (inbound transactions are routed to one of two pipes, based upon the
bridge’s Hub ID). For almost all cases, this is acceptable, as the traffic patterns on each PCI bus
are unrelated. In a peer-to-peer scenario, this is not valid.
4.5.4 Master Abort / Target Abort Completions on Hub Interface
Though the P64H2’s primary bus is the hub interface, from a register and software perspective, the
hub interface is a PCI-X bus and the P64H2 is a PCI-X bridge that supports a secondary bus
configured as either PCI or PCI-X.
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0 Section 8.7.1.5 modified
the behavior of a bridge from that specified in the PCI-to-PCI Bridge Architecture Specification,
Revision 1.1 regarding returning completions on the primary bus when the secondary bus
transaction terminates in either a master abort or target abort. In general, the PCI-X Addendum to
the PCI Local Bus Specification, Revision 1.0 does not honor the Master Abort Mode bit for
cycles requiring completions, and returns to the primary bus the termination that occurred on the
secondary bus without any translation.
4.5.4.1
Behavior of Hub Interface Initiated Cycles to PCI/PCI-X Receiving
Immediate Terminations
The behavior described for completion required cycles is independent of the setting of the Master
Abort Mode bit, and is independent of whether the cycle is exclusive (locked) or not. The P64H2
returns all 1s on data bytes for a read completion that terminates in either Master Abort or Target
Abort.
Table 50. Immediate Terminations of Completion Required Cycles to PCI/PCI-X
PCI/PCI-X Termination
Successful
Master Abort
Hub Interface Completion
Successful
Master Abort
Target Abort
Target Abort
Status Register Bits Set
• Master Data Parity Error (Sec) ¹
• Received Master Abort (Sec)
• Received Target Abort (Sec)
• Signaled Target Abort (Pri)
• Master Data Parity Error (Sec) ¹
NOTES:
1. The Master Data Parity Error bit is set only if a data parity error was encountered on the PCI/PCI-X bus.
Intel^® 82870P2 P64H2 Datasheet
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