82870P2P64H2 Datasheet, PDF (125/217 Pages) –

Functional Description
R
4.2.2 Attributes
Table 24 describes how the P64H2 fills in attribute fields where the PCI-X Addendum to the PCI
Local Bus Specification, Revision 1.0 leaves some implementation leeway.
Table 24. Intel® P64H2 Implementation of Requester Attribute Fields
Attribute
No Snoop (NS)
Relaxed
Ordering (RO)
Tag
Byte Counts
Function
As a target, this bit is forwarded with the transaction to allow the MCH to not snoop the
transaction. It goes to bit 1 in the TD Attribute field of the hub interface packet. It is not
generated by the Intel® P64H2 as a master from a hub interface packet. The P64H2
takes no action on this bit.
This bit allows relaxed ordering of transactions, which the P64H2 does not permit. This
bit is forwarded in the P64H2 and is never generated on PCI-X from a hub interface
packet.
Since the P64H2 only has one outstanding request on PCI-X at a time, this field is
always set to 0.
From the hub interface, this is based upon the length field from the hub interface, which
is DWord based.
4.2.3
Burst Transactions
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0 allows burst transactions
to cross page (in the P64H2’s case, this is 4 KB) and 4 GB address boundaries. As a PCI-X
master, the P64H2 will always end the transaction at a 4 KB boundary. As a PCI-X target, the
P64H2 will allow a burst past a 4 KB page boundary.
The P64H2 never issues an immediate response as a target for a burst read command, but it must
be ready with 128 bytes of data space (an ADQ) as an initiator. If it does not have this space
available, it does not issue the transaction.
4.2.4 Device Select Timing
PCI-X targets are required to claim transactions by asserting PxDEVSEL# as shown in Table 25.
The P64H2 always responds as a type A target.
Table 25. DEVSEL# Timing
Decode Speed
1 clock after address phase(s)
2 clocks after address phase(s)
3 clocks after address phase(s)
4 clocks after address phase(s)
5 clocks after address phase(s)
6 clocks after address phase(s)
PCI-X
Not Supported
Decode A
Decode B
Decode C
N/A
Subtractive
Intel^® 82870P2 P64H2 Datasheet
125