82870P2P64H2 Datasheet, PDF (98/217 Pages) –

Register Description
R
3.4.1.6
3.4.1.7
3.4.1.8
CC—Class Code Register (D28,30: F0)
Offset:
09–0Bh
Default Value: 080020h
Attribute:
Size:
RO
24 bits
This register contains the base class, sub-class and programming interface codes.
Bits
23:16
15:8
7:0
Description
Base Class Code (BCC).
08h = Generic system peripheral.
Sub Class Code (SCC).
00h = Generic peripheral is an interrupt controller.
Programming Interface (PIF).
20h = Interrupt peripheral is an I/OxAPIC.
HDR—Header (D28,30: F0)
Offset:
0C–0Fh
Default Value: 00000000h
Attribute:
Size:
RO
32 bits
This is additional header information related to the I/OxAPIC.
Bits
31:24
23:16
15:8
7:0
Description
Built In Self Test (BIST). Reserved
Header Type (HTYPE). This indicates that it is a type 00 header (normal PCI device) and that it
is a single function device.
Latency Timer (LAT). Reserved
Cache Line Size (CLS). Reserved
MBAR—Memory Base Register (D28,30: F0)
Offset:
10–13h
Default Value: 00000000h
Attribute:
Size:
R/W, RO
32 bits
This register contains the APIC Base Address for the APIC memory space.
Bits
31:12
11:4
3
2:1
0
Description
Address (ADDR)—R/W. These bits determine the base address of the I/OxAPIC
Reserved
Prefetchable (PF)—RO. Hardwired to 0; indicates that the BAR is not prefetchable.
Location (LOC)—RO. Hardwired to 00; indicates that the address can be located anywhere in
the 32-bit address space.
Space Indicator (SI)—RO. Hardwired to 0; indicates that the BAR is in memory space.
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Intel^® 82870P2 P64H2 Datasheet