82870P2P64H2 Datasheet, PDF (6/217 Pages) –

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3.4.3 Indirect Memory Space Registers....................................................... 103
3.4.3.1 ID—APIC ID Register (D28,30: F0)................................... 103
3.4.3.2 VS—Version Register (D28,30: F0) .................................. 104
3.4.3.3 ARBID—Arbitration ID Register (D28,30: F0) ................... 104
3.4.3.4 BCFG—Boot Configuration Register (D28,30: F0) ........... 105
3.4.3.5 RDL—Redirection Table Low DWord Register
(D28,30: F0) ...................................................................... 105
3.4.3.6 RDH—Redirection Table High Register (D28,30: F0)....... 106
3.5 SMBus Interface................................................................................................. 107
3.5.1 CMDSTS—Command / Status Register............................................. 108
3.5.2 BNUM—Bus Number Register ........................................................... 109
3.5.2.1 DFNUM—Device / Function Number Register.................. 109
3.5.3 RNUM—Register Number .................................................................. 109
3.5.3.1 DATA—Data Register ....................................................... 110
3.5.4 CFG—SMBus Configuration Register ................................................ 110
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Functional Description .................................................................................................... 112
4.1 PCI Interface ...................................................................................................... 112
4.1.1 Summary of Changes ......................................................................... 112
4.1.2 Transaction Types .............................................................................. 113
4.1.3 Detection of 64-bit Environment ......................................................... 113
4.1.4 Data Bus ............................................................................................. 114
4.1.5 Read Transactions.............................................................................. 115
4.1.6 Configuration Transactions................................................................. 115
4.1.7 Transaction Termination..................................................................... 118
4.1.8 Lock Cycles ........................................................................................ 119
4.1.9 Error Handling..................................................................................... 119
4.1.9.1 Address Parity Errors ........................................................ 120
4.1.9.2 Data Parity Errors .............................................................. 121
4.1.9.3 Hub Interface Configuration Write Transactions ............... 121
4.1.9.4 Read Transactions from Hub Interface Targeting PCI...... 121
4.1.9.5 Read Transactions from PCI Targeting Hub Interface...... 121
4.1.9.6 Write Transactions on Hub Interface
(Intel^® P64H2 As Hub Interface Target) ............................ 122
4.1.9.7 Write Transactions on Hub Interface
(Intel^® P64H2 As Hub Interface Master)............................ 122
4.1.9.8 Write Transactions on PCI
(Intel^® P64H2 As PCI Target)............................................ 122
4.1.9.9 Write Transactions on PCI
(Intel^® P64H2 As PCI Master) ........................................... 122
4.1.9.10 System Errors.................................................................... 123
4.1.9.11 PCI SERR# Pin Assertion ................................................. 123
4.1.9.12 Other System Errors.......................................................... 123
4.2 PCI-X Interface................................................................................................... 124
4.2.1 Command Encoding ........................................................................... 124
4.2.2 Attributes............................................................................................. 125
4.2.3 Burst Transactions.............................................................................. 125
4.2.4 Device Select Timing .......................................................................... 125
4.2.5 Wait States ......................................................................................... 126
4.2.6 Split Transactions ............................................................................... 126
4.2.6.1 Completer Attributes.......................................................... 126
4.2.6.2 Requirements for Accepting Split Completions................. 126
4.2.6.3 Split Completion Messages............................................... 126
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Intel^® 82870P2 P64H2 Datasheet