82870P2P64H2 Datasheet, PDF (8/217 Pages) –

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4.5 Transaction Ordering ......................................................................................... 156
4.5.1 Comparison of Rules vs A PCI–PCI Bridge........................................ 156
4.5.2 Ordering Relationships ....................................................................... 156
4.5.3 Hub Interface Fence Special Cycle .................................................... 157
4.5.4 Master Abort / Target Abort Completions on Hub Interface ............... 157
4.5.4.1 Behavior of Hub Interface Initiated Cycles to
PCI/PCI-X Receiving Immediate Terminations ................. 157
4.5.4.2 Behavior of Hub Interface Initiated Cycles PCI-X
Receiving Split Terminations............................................. 158
4.5.4.3 Hub Interface Action on Immediate Responses to
PCI-X Split Completions.................................................... 159
4.5.4.4 Behavior of PCI/PCI-X Initiated Cycles to Hub Interface... 159
4.6 I/OxAPIC Interrupt Controller (Device 30 and 28) .............................................. 160
4.6.1 Interrupt Insertion................................................................................ 160
4.6.1.1 Pin Interrupts ..................................................................... 160
4.6.1.2 Message Signaled Interrupts (MSI)................................... 160
4.6.2 Interrupt Delivery................................................................................. 160
4.6.2.1 Front-Side Interrupt Delivery ............................................. 160
4.6.3 Buffer Flushing.................................................................................... 162
4.6.4 Boot Interrupt ...................................................................................... 162
4.7 SMBus Interface................................................................................................. 163
4.7.1 SMBus Signaling................................................................................. 163
4.7.1.1 Waveforms ........................................................................ 164
4.7.1.2 Architecture ....................................................................... 166
4.7.1.3 Data Transfer Examples ................................................... 168
4.7.1.4 Configuration Space Registers.......................................... 169
4.7.1.5 Memory Space Registers .................................................. 169
4.7.2 Configuration Access Arbitration ........................................................ 170
4.8 System Setup ..................................................................................................... 171
4.8.1 Clocking .............................................................................................. 171
4.8.2 Component Reset............................................................................... 172
4.8.2.1 Software PCI Reset........................................................... 172
4.8.2.2 RSTIN#.............................................................................. 173
4.8.2.3 PowerOK ........................................................................... 173
4.8.3 I/OxAPIC System Assumptions .......................................................... 174
4.9 Reliability, Availability, and Serviceability (RAS)................................................. 175
4.9.1 Error Types ......................................................................................... 176
4.9.2 Error Logging ...................................................................................... 176
4.9.3 Logged Errors ..................................................................................... 178
4.9.4 Allowable Error Combinations for RAS_STS...................................... 178
4.9.5 Data Poisoning ................................................................................... 179
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Intel^® 82870P2 P64H2 Datasheet