82870P2P64H2 Datasheet, PDF (18/217 Pages) –

Introduction
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The PCI Bus interface is compliant with the PCI Local Bus Specification, Revision 2.2. The PCI-X
interface is compliant with the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0.
PCI-X provides enhancements over PCI that enable faster and more efficient data transfers. For
PCI Mode, the P64H2 supports PCI bus frequencies of 33 MHz and 66 MHz. For the PCI-X
mode, the P64H2 supports PCI bus frequencies of 66 MHz, 100 MHz, and 133 MHz. Four PCI
bus slots are supported at 33 MHz and 66 MHz, two slots are supported at 100 MHz, and one slot
is supported at 133 MHz.
Hot Plug Controller
The P64H2 hot plug controller allows PCI card removal, replacement, and addition without
powering down the system. The P64H2 hot plug controller resides in Function 0 of the secondary
bus device 31. It supports three to six PCI slots through an input/output serial interface when
operating in Serial Mode, and one to two slots through an input/output parallel interface when
operating in Parallel Mode. The input serial interface is polling and is in continuous operation. The
output serial interface is “demand” and acts only when requested. These serial interfaces run at
about 8.25 MHz regardless of the speed of the PCI bus. In parallel mode, the P64H2 performs the
serial-to-parallel conversion internally, so the serial interface cannot be observed. However,
internally the hot plug controller always operates in a serial mode.
I/O APIC
The P64H2 contains two I/O APIC controllers (I/OxAPIC where x=A or B), both of which reside
on the primary bus. The intended use of these controllers is to have the interrupts from PCI Bus A
connected to the interrupt controller on device 28, and have the interrupts on PCI Bus B connected
to the interrupt controller on device 30.
SMBus Interface
The System Management Bus (SMBus) is a two-wire interface through which various system
devices (e.g., the P64H2) can communicate with each other and with the rest of the system. It is
based on the principles of I²C.
The SMBus controller has access to all internal registers. It can perform reads and writes from all
registers through the particular interface’s configuration space. Hot plug and I/O APIC memory
spaces are accessible through their respective configuration spaces. The reason for the SMBus
interface is to access registers when the system may be unstable or locked, which can result with
broken queues. Any register access through SMBus must be able to proceed while the system is
stuck.
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Intel^® 82870P2 P64H2 Datasheet