82870P2P64H2 Datasheet, PDF (69/217 Pages) –

Register Description
R
3.2.48.3
PC100—Prefetch Control for 100 MHz Register (D29,31: F0)
Offset:
FC–FDh
Default Value: 7B7Bh
Attribute:
Size:
R/W
16 bits
Bits
Description
15:12
11:8
7:4
3:0
Subsequent Threshold (TS). This field represents the subsequent threshold size in 64-byte
cache lines.
Subsequent Request (RS). This field represents the subsequent request size in 64-byte cache
lines.
Initial Threshold (TI). This field represents the initial threshold size in 64-byte cache lines.
Initial Request (RI). This field represents the initial request size in 64-byte cache lines.
3.2.48.4
PC133—Prefetch Control for 133 MHz Register (D29,31: F0)
Offset:
FE–FFh
Default Value: BFFFh
Attribute:
Size:
R/W
16 bits
Bits
Description
15:12
11:8
7:4
3:0
Subsequent Threshold (TS). This field represents the subsequent threshold size in 64-byte
cache lines.
Subsequent Request (RS). This field represents the subsequent request size in 64-byte cache
lines.
Initial Threshold (TI). This field represents the initial threshold size in 64-byte cache lines.
Initial Request (RI). This field represents the initial request size in 64-byte cache lines.
Intel^® 82870P2 P64H2 Datasheet
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