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82870P2P64H2 Datasheet, PDF (108/217 Pages) –
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Register Description
R
3.5.1
CMDSTS—Command / Status Register
Offset:
00h
Default Value: 00h
Attribute:
Size:
R/W, RO
8 bits
When written, this is the Command Register. When read, this is the Status Register. All
configuration accesses from the SMBus port are initiated by writing to this register. While a
command is in progress, all future writes or reads will be NACK’d by the P64H2 to avoid having
registers overwritten.
Bits
Description
Error (ERR)—RO.
7
0 = No error (default)
1 = Indicates that the previous command terminated abnormally. This bit will be set if a master
or target abort occurred on the SMBus initiated access.
6:4 Reserved
Configuration Accesses Enable (EN)—R/W.
3
1 = Enable. Must be set to 1 to enable the configuration accesses from the SMBus Port.
0 = Disable. (default)
Command (CMD)—R/W. These bits represent the command that is to be performed. The
encodings are as follows:
000 = NOP: Normal Power-up State for the register. (default)
001 = Write Byte: Writes the byte in the Data Register bits [7:0] to the configuration location
specified by the Bus Number, Device/Function and Register Number registers.
010 = Write Word: Writes the bytes in the Data Register bits [15:0] to the configuration location
specified by the Bus Number, Device/Function and Register Number registers. The
Register Number [0] bit is ignored for this operation, all word writes must be aligned on a
2:0
word boundary.
011 = Write DWord: Writes the bytes in the Data Register [31:0] to the configuration location
specified by the Bus Number, Device/Function and Register Number registers. The
Register Number [1:0] bits are ignored for this operation, all DWord writes must be aligned
on a DWord boundary.
100 = Read DWord: Reads the configuration location specified by the Bus Number,
Device/Function and Register Number registers to the Data Register [31:0]. The Register
Number [1:0] bits are ignored for this operation, all DWord reads must be aligned on a
DWord boundary.
108
Intel® 82870P2 P64H2 Datasheet
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