82870P2P64H2 Datasheet, PDF (45/217 Pages) –

Register Description
R
Bits
Description
Received System Error (RSE)—R/WC.
0 = No SERR# received.
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1 = P64H2 sets this bit when a SERR# assertion is received on PCI.
Note: Software clears this bit by writing a 1 to it.
Received Master Abort (RMA)—R/WC.
0 = No master abort received.
1 = P64H2 is acting as an initiator on the PCI bus and the cycle is master-aborted. For hub
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interface packets that have completion required, this should also cause a target abort
completion status to be returned and set the Signaled Target Abort bit in the PCI Primary
Device Status (PD_STS) Register.
Note: Software clears this bit by writing a 1 to it.
Received Target Abort (RTA)—R/WC.
0 = No target abort received.
1 = P64H2 is acting as an initiator on PCI and a cycle is target-aborted on PCI. For "completion
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required" hub interface packets, this event should force a completion status of "target abort"
on the hub interface, and set the Signaled Target Abort in the PCI Primary Device Status
(PD_STS) Register.’
Note: Software clears this bit by writing a 1 to it.
Signaled Target Abort (STA)—R/WC.
0 = No target abort signaled.
11
1 = P64H2 is acting as a target on the PCI Bus and signals a target abort.
Note: Software clears this bit by writing a 1 to it.
10:9
DEVSEL# Timing (DVT)—RO. Hardwired to 01. This field indicates that the P64H2 responds in
medium decode time to all cycles targeting the hub interface.
Data Parity Error Detected. (DPD)—R/WC.
0 = No data parity error detected.
1 = P64H2 sets this bit when all of the following is true:
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• The P64H2 is the initiator on PCI.
• PxPERR# is detected asserted or a parity error is detected internally
• The Parity Error Response Enable bit in the Bridge Control Register (bit 0, offset 3Eh) is
set.
Note: Software clears this bit by writing a 1 to it.
7
Fast Back-to-Back Capable (FBC)—RO. Hardwired to 1; indicates that the secondary interface
of the P64H2 can receive fast back-to-back cycles.
6
Reserved
5
66 MHz Capable (C66)—RO. Hardwired to 1; indicates the secondary interface of the bridge is
66 MHz capable.
4:0 Reserved
Intel^® 82870P2 P64H2 Datasheet
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