82870P2P64H2 Datasheet, PDF (106/217 Pages) –

Register Description
R
3.4.3.6
Bits
Description
Interrupt Input Pin Polarity (IP)—R/W. This bit specifies the polarity of each interrupt signal
connected to the interrupt pins.
13
0 = Active high. (default)
1 = Active low.
Delivery Status (DS)—RO. This field contains the current status of the delivery of this interrupt.
It is read only. Writes to this bit have no effect.
12 0 = Idle; no activity for this interrupt (default)
1 = Pending; interrupt has been injected, but delivery is held up due the inability of the receiving
APIC unit to accept the interrupt at this time.
Destination Mode (DSTM)—R/W. This field determines the interpretation of the Destination
field.
11 0 = Physical; Destination APIC ID is identified by RDH bits [59:56]. (default)
1 = Logical; Destination is identified by matching bits [63:56] with the Logical Destination in the
Destination Format Register and Logical Destination Register in each local APIC.
Delivery Mode (DELM)—R/W. This field specifies how the APICs listed in the destination field
should act when the interrupt is received. Certain Delivery Modes will only operate as intended
when used in conjunction with a specific trigger mode. These encodings are described in more
detail in each serial message. The encodings are:
000 = Fixed: Trigger Mode can be edge or level. (default)
001 = Lowest Priority: Trigger Mode can be edge or level.
10:8 010 = SMI/PMI: Not supported
011 = Reserved
100 = NMI: Not supported
101 = INIT: Not supported
110 = Reserved
111 = ExtINT: Not supported
7:0
Vector (VCT)—R/W. This field contains the interrupt vector for this interrupt. Values range
between 10h and FEh. (default=00h)
RDH—Redirection Table High Register (D28,30: F0)
Offset:
11h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
The information in this register is sent on the system bus to address a local APIC. There is one
RDH Register for every interrupt. The first interrupt (pin 0) has this entry at offset 11h. The
second interrupt at 13h, third at 15h, etc. until the final interrupt (interrupt 23) at 3Fh.
Bits
Description
31:24
23:16
15:0
Destination ID (DID). This information is transferred in bits [19:12] of the address.
Extended Destination ID (EDID). These are bits [11:4] of the address.
Reserved
106
Intel^® 82870P2 P64H2 Datasheet