82870P2P64H2 Datasheet, PDF (152/217 Pages) –

Functional Description
R
4.4
Addressing
4.4.1 I/O Window Addressing
This section describes the I/O window that can be set up in the bridge. (Section 4.4.3 outlines the
I/O cycles in the VGA range). The register bits listed below also modify the response by the
P64H2 to I/O transactions:
• I/O Base and Limit Address Registers
• I/O Enable bit in the PCI Primary Device Command (PD_CMD) Register
• Master Enable bit in the PCI Primary Device Command (PD_CMD) Register
• Enable 1 KB granularity in the P64H2 Configuration Register
To enable outbound I/O transactions, the I/O Enable bit (bit 0) must be set in the PD_CMD
Register in the P64H2 configuration space (offset 04–05h). If the I/O Enable bit is not set, all I/O
transactions initiated on the hub interface will receive a master abort completion. No inbound I/O
transactions may cross the bridge and are therefore master aborted.
The P64H2 implements one set of I/O Base and Limit Address Registers in configuration space
that define an I/O address range for the bridge. Hub interface I/O transactions with addresses that
fall inside the range defined by the I/O Base and Limit Address Registers are forwarded to PCI,
and PCI I/O transactions with addresses that fall outside this range are master aborted.
Setting the base address to a value greater than that of the limit address turns off the I/O range.
When the I/O range is turned off, no I/O transactions are forwarded to PCI even if the I/O enable
bit is set. The I/O range has a minimum granularity of 4 KB and is aligned on a 4 KB boundary.
The maximum I/O range is 64 KB. This range may be lowered to 1 KB granularity by setting the
EN1K bit in the P64H2 Configuration Register at offset 40h.
The base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at
address 30h. The top 4 bits of the 8-bit field define bits [15:12] of the I/O base address. The
bottom 4 bits are read only; returning value 0h to indicate that the P64H2 supports 16-bit I/O
addressing. Bits [1:0] of the base address are assumed to be 0,which naturally aligns the base
address to a 4 KB boundary. The I/O base upper 16 bits register at offset 30h is reserved. Reset
initializes the value of the I/O base address to 0000h.
The I/O limit register consists of an 8-bit field at offset 1Dh and a16-bit field at offset 32h. The top
4 bits of the 8-bit field define bits [15:12] of the I/O limit address. The bottom 4 bits are read only,
returning value 0h to indicate that 16-bit I/O addressing is supported. Bits [11:0] of the limit
address are assumed to be FFFh, which naturally aligns the limit address to the top of a 4 KB I/O
address block. The 16 bits contained in the I/O limit upper 16 bits register at offset 32h are
reserved. Reset initializes the value of the I/O limit address to 0FFFh.
Note:
If the EN1K bit is set in the P64H2 Configuration Register, the Base and Limit Registers are
changed such that the top 6 bits of the 8-bit field define bits [15:10] of the I/O base/limit address,
and the bottom 2 bits read only as 0h to indicate support for 16-bit I/O addressing. Bits [9:0] are
assumed to be 0 (for the base register) and 1 (for the limit register), which naturally aligns the
address to a 1 KB boundary.
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Intel^® 82870P2 P64H2 Datasheet