82870P2P64H2 Datasheet, PDF (22/217 Pages) –

Signal Description
R
Signal
PAIRDY#
PATRDY#
PASTOP#
PAPERR#
PASERR#
PAREQ[5:0]#
PAGNT[5:0]#
PAM66EN
PA_133EN
PAPCIXCAP
PAPLOCK#
Type
Description
Initiator Ready: PAIRDY# indicates the ability of the initiator to complete the
I/O current data phase of the transaction. A data phase is completed when both
PAIRDY# and PATRDY# are sampled asserted.
Target Ready: PATRDY# indicates the ability of the target to complete the
current data phase of the transaction. A data phase is completed when both
I/O PATRDY# and PAIRDY# are sampled asserted. PATRDY# is tri-stated from the
leading edge of PCIRST#. PATRDY# remains tri-stated by the P64H2 until
driven as a target.
I/O
Stop: PASTOP# indicates that the target is requesting an initiator to stop the
current transaction.
Parity Error: PAPERR# is driven by an external PCI device when it receives
I/O data that has a parity error. Driven by the P64H2 when, as an initiator it detects
a parity error during a read transaction and as a target during write transactions.
System Error: PASERR# can be pulsed active by any PCI device that detects
I a system error condition except the P64H2. The P64H2 samples PASERR# as
an input and conditionally forwards it to the hub interface.
PCI Requests: PAREQ[5:0]# supports up to six masters on the PCI bus. The
I P64H2 accepts six request inputs, PAREQ[5:0]# into its internal bus arbiter. The
P64H2 request input to the arbiter is an internal signal.
PCI Grants: PAGNT[5:0]# supports up to six masters on the PCI bus. The
arbiter can assert one of the six bus grant outputs, to indicate that an initiator
can start a transaction on the PCI Bus.
O
PAGNT [3] - 66/200 MHz Clocking Strap: When this pin is sampled high (logic
1) on PWROK, the P64H2 uses the 200 MHz differential clock. When this pin is
sampled low (logic 0) on PWROK, the P64H2 uses the 66 MHz clock input.
66 MHz Enable: This input signal from the PCI Bus indicates the speed of the
PCI Bus. If it is high, the bus speed is 66 MHz; if it is low, the bus speed is
33 MHz. This signal will be used to generate the appropriate clock (33 MHz or
66 MHz) on the PCI Bus.
If Hot plug is enabled, the PCI bus will power-up as 33 MHz PCI and the P64H2
I/O will drive this pin low. Also, if software ever writes 00 to the PFREQ Register,
the P64H2 will drive this pin low.
If Hot plug is not enabled at power-up or if software never writes 00 to the
PFREQ Register, the P64H2 tri-states this pin. Additionally, if the hot plug mode
is single slot with no glue, the P64H2 tri-states this pin, regardless of the setting
of the PFREQ Register. The system board will pull this pin to a logic 1.
Enable PCI-X at 133 MHz for PCI Bus A: This pin, when high, allows the
I
PCI-X segment to run at 133 MHz when PA_PCIXCAP is sampled high. When
low, the PCI-X segment will only run at 100 MHz when PA_PCIXCAP is
sampled high.
I
PCI-X Capable: This signal indicates whether all devices on the PCI bus are
PCI-X devices, so that the P64H2 can switch into PCI-X mode.
PCI Lock: This signal indicates an exclusive bus operation and may require
O
multiple transactions to complete. The P64H2 asserts PLOCK# when it is doing
exclusive transactions on PCI. PLOCK# is ignored when PCI masters are
granted the bus. The P64H2 does not propagate locked transactions upstream.
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Intel^® 82870P2 P64H2 Datasheet