82870P2P64H2 Datasheet, PDF (199/217 Pages) –

Electrical Characteristics
R
Symbol
CLK133
Parameter
Min
Max
Units
Notes
Tperiod
Trise
Tfall
—
—
Tccjitter
—
—
—
—
—
CLK33
Average Period
Rise time across 600 mV
Fall time across 600 mV
Rise/Fall Matching
Cross point at 1V
Cycle to Cycle jitter
Duty Cycle
Maximum voltage allowed at input
Minimum voltage allowed at input
Rising edge ringback
Falling edge ring back
7.5
7.65
ns
6
300
600
ps
7,8
300
600
ps
7,8
20%
7,9
0.51
0.76
V
200
ps
45
55
%
1.45
V
-200
mV
0.85
V
0.35
V
Tperiod
Thigh
Tlow
—
—
Trise
Tfall
APICCLK
CLK period
CLK high time
CLK low time
Rising edge rate
Falling edge rate
CLK rise time
CLK fall time
30.0
N/A
ns
1,2
12.0
N/A
ns
3
12.0
N/A
ns
4
1.0
4.0
V/ns 5
1.0
4.0
V/ns 5
0.5
2.0
ns
5
0.5
2.0
ns
5
fioap
Thigh
Tlow
Trise
Tfall
Operation Frequency
High time
Low time
Rise time
Fall time
14.32
12
12
1.0
1.0
33.33
36
36
5.0
5.0
MHz
ns
ns
ns
ns
NOTES:
1. Period, jitter, offset and skew measured on rising edge @ 1.5 V for 3.3 V clocks.
2. The average period over any 1 us period of time must be greater than the minimum specified period.
3. Thigh is measured at 2.4 V for non-host outputs.
4. Tlow is measured at 0.4 V for all outputs.
5. For 3.3 V clocks Trise and Tfall are measured as a transition through the threshold region Vol = 0.4 V and
Voh = 2.4 V (1 mA) JEDEC Specification.
6. Measured at crossing point.
7. Measured from Vol = 0.2 V to Voh = 0.8 V.
8. Still simulating to determine [0.2–0.8 V] or [0.3–0.9 V].
9. Determined as a fraction of 2*(Trise – Tfall) / (Trise + Tfall).
Intel^® 82870P2 P64H2 Datasheet
199