82870P2P64H2 Datasheet, PDF (129/217 Pages) –

Functional Description
R
4.2.11
Bridge Buffer Requirements
The P64H2 always has 128 bytes (1 ADQ) available for accepting memory write, split completion,
and immediate read data. The P64H2 contains 1.5 KB of data total for inbound transactions.
The P64H2 PCI-X interface terminates all memory transactions (Memory Read DWord, Memory
Read Block, and Alias to Memory Read Block) that address the MCH with a Split Response.
Other split transaction commands are not decoded by the P64H2.
The P64H2 does not implement any split completion buffer allocation algorithm as listed in the
PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0. This is not necessary. The
P64H2 never requests, on the hub interface, more than it has buffer space for on returns, and does
not initiate a cycle from the hub interface that it cannot accept as a return. The bridge rules of the
specification already allow the PCI-X interface to retry split completions if the bridge is
temporarily full.
Therefore, the split transaction control registers are not used by the P64H2.
4.2.12 Cycle Translation Between Interfaces
4.2.12.1 Conventional PCI to PCI-X / Hub Interface
Table 30. Conventional PCI to PCI-X / Hub Interface
Conventional PCI Command
I/O Read / Write
Configuration Read / Write
Memory Read, Memory read line,
memory read multiple
Memory Write
Memory Write and Invalidate
PCI-X as Target
Hub Interface as Target
Master Abort at source (not supported)
Master Abort at source (not supported)
Forward to hub interface unless
the peer mode test bit is set
Memory Read
Memory Write
Memory Write
Memory Write
Memory Write
The attribute phase on the PCI-X transfer has the following characteristics:
• The P64H2 uses the primary bus number as its Bus Number
• Sets the Device Number and Function Number fields to 0
• Clears the Relaxed Order or No Snoop attribute bits on transactions forwarded from a
conventional bus.
Intel^® 82870P2 P64H2 Datasheet
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