82870P2P64H2 Datasheet, PDF (65/217 Pages) –

Register Description
R
Bits
Description
Synchronous PXPCLKI to CLK66 (SYNCPH).
0 = PCI/PCI-X input clock will be considered asynchronous.
1 = If 1, the PCI/PCI-X input clock, PXPCLKI, will be considered a synchronous clock relative to
4
the hub interface input clock, CLK66.
Note: This bit must not be set to 1 if operating in 100 MHz or 133 MHz mode. It may be set to 0
if operating at 33 MHz or 66 MHz mode and if the clock meets the requirements laid out
in Section 4.8.
Maximum Outstanding Requests (MAXR). Only the value from PCI bus A (Device 31) will be
used. This field specifies the maximum number of completion required requests the P64H2 can
issue on the hub interface.
0000 = 1 request
3:0 _{0001 = 2 requests}
0010 = 3 requests
…
1111 = 16 requests (default)
Intel^® 82870P2 P64H2 Datasheet
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