82870P2P64H2 Datasheet, PDF (84/217 Pages) –

Register Description
R
3.3.2.1
3.3.2.2
GPT—General Purpose Timer Register
Offset:
00h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This 8-bit register has no functionality but is preserved as read/write for software compatibility.
Bits
Description
7:0 Reserved, maintained for software compatibility
SE—Slot Enable Register
Offset:
01h
Default Value: 00h
Attribute:
Size:
R/W
8 bits
These bits control the enabling and disabling of slots. If this register has been changed before the
SOGO bit in the Hot Plug Miscellaneous Register is set, then a four-phase output sequence is used
to set the states of the RESET#, CLKEN#, BUSEN# and PWREN signals to the slots after the
write to set SOGO is completed.
If the value of one of these bits changes from 0 to 1 when SOGO is set, the four-step slot enable
sequence is used to power up the slot. If a stored bit changes from 1 to 0, the four-step slot disable
sequence is used to power down that slot. If some bits have changed from 0 to 1, and others
change from 1 to 0 when SOGO bit is set, the appropriate slots are disabled first. After the disable
sequence has been executed, an enable sequence is executed to enable the appropriate slots. These
bits cannot be written to 1 as long as the corresponding slot switch is open.
The current value of this register can be read back at any time, but may not indicate the current
state of the slots if the SOGO bit has not yet been written.
Bits
Description
7:6 Reserved
Enable Slot (ES)—R/W, RO. When set, the slot is to be enabled. Bit 5 corresponds to slot F, bit
5:0
4 to slot E, etc. until bit 0, which corresponds to slot A. These bits are R/W only for slots enabled
by the HPx_SLOT[2:0] power on straps. Otherwise, they are RO for the disabled slots. These bits
are also RO for a slot when it’s associated switch input is in an open state.
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Intel^® 82870P2 P64H2 Datasheet