82870P2P64H2 Datasheet, PDF (29/217 Pages) –

Signal Description
R
2.4
Interrupt Interface
This section lists the interrupt interface signals. There are two sets of IRQ interrupt signals;
PAIRQ[15:0] for PCI Bus A and PBIRQ[15:0] for PCI Bus B.
Table 8. Interrupt Interface Signals
Signal
PAIRQ[15:0]
PBIRQ[15:0]
BT_INTR#
APICCLK
APICD[1:0]
Type
Description
Interrupt Request Bus A: The PIRQ# lines from PCI interrupts PIRQ[A:D] can
I be routed to these interrupt lines. PAIRQ[15:0] are connected to an I/OxAPIC
that resides on PCI bus A (pins [15:0]).
Interrupt Request Bus B: The PIRQ# lines from PCI interrupts PIRQ[A:D] can
I be routed to these interrupt lines. PBIRQ[15:0] are connected to an I/OxAPIC
that resides on PCI bus B (pins [15:0]).
Boot Interrupt: This open drain output is a logical OR of all interrupt request
inputs from both I/OxAPICs. These pins may be connected to the ICH to support
O ^{connecting boot devices behind the Intel® P64H2 to an 8259.}
Each interrupt is qualified with the mask. If the interrupt is masked, it goes out
on the BT_INTR# pin.
APIC Clock: This clock is 16.66667 MHz and is the APIC bus clock. The
I frequency of this clock can be raised to as high as 33 MHz to support FRC
mode on dual-processor systems.
APIC Data: These bi-directional open drain signals are used to send and
I/O receive data over the APIC bus. As inputs the data is valid on the rising edge of
APICCLK. As outputs, new data is driven from the rising edge of the APICCLK.
2.5
Hot Plug Interface
There are two sets of hot plug interface signals; one for PCI Bus A and one for PCI Bus B.
Table 9. Hot Plug Interface A Signals
Signal
HPA_SIC
HPA_SIL#
HPA_SID
HPA_SOR#
HPA_SORR#
Type
O
O
I
O
O
Description
Serial Input Clock: This signal is normally high. It pulses low to shift
external serial input shift register data one bit position. (The shift
registers should be similar to standard “74x165” series).
Serial Input Load: This signal is normally high. It pulses low to
synchronously parallel load external serial input shift registers on the next
rising edge of HPA_SIC.
Serial Input Data: Data shifted in from external logic on HPA_SIC.
Serial Output Non-Reset Latch Clear: This signal is normally high. It
asynchronously clears the power-enable, clock-enable, slot bus-enable,
and LED latches.
Serial Output Reset Latch Clear: This signal is normally high. It
asynchronously clears the PCI slot reset latches.
Intel^® 82870P2 P64H2 Datasheet
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