82870P2P64H2 Datasheet, PDF (164/217 Pages) –

Functional Description
R
4.7.1.1 Waveforms
The timing relationship between SDA and SCL is shown in Figure 5. Note that the SDA value
must be valid through the duration of SCL being in the high state.
Figure 5. Basic SMBus Transfer Waveform
SCL
SDA
Valid
Valid
Valid
SMBus_Transfer
Start Phase
A start condition is generated when SMBus is idle to indicate that its state is changing to busy. The
start condition occurs when SDA transitions from high-to-low while SCL remains high. The
SMBus protocol also allows a master to “Repeat Start”, meaning that a new transfer is started by
the same master, without a stop condition.
Figure 6. Start (S) / Repeat Start (Sr) Signaling
SCL
SDA
SMBus_Transfer_Start
Stop Phase
A stop condition is generated when SMBus is busy to indicate that its state is changing to idle. The
Stop condition occurs when SDA transitions from low-to-high while SCL remains high.
Figure 7. Stop (P) Signaling
SCL
SDA
A stop bit can occur at any point in a data stream. It is not guaranteed to occur after an ACK from
a target (as later waveforms will show). The P64H2 must be able to accept a stop condition at any
time and clean up.
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Intel^® 82870P2 P64H2 Datasheet