82870P2P64H2 Datasheet, PDF (158/217 Pages) –

Functional Description
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Table 51. Immediate Terminations of Posted Write Cycles to PCI/PCI-X
PCI/PCI-X Termination
MAM Bit
Hub Interface Cycle
Status Register Bits Set
Successful
Master Abort
Master Abort
Target Abort
N/A
None
• None
1
DO_SERR ¹
• Received Master Abort (Sec)
• Signaled System Error (Pri) ¹
0
None
• Received Master Abort (Sec)
• Received Target Abort (Sec)
N/A
DO_SERR ¹
• Signaled System Error (Pri) ¹
NOTES:
1. The SO_SERR cycle and setting of the Signaled System Error bit only occur if the SERR# Enabled in
the PCI Primary Device Command Register is set.
4.5.4.2
Behavior of Hub Interface Initiated Cycles PCI-X Receiving Split
Terminations
The behavior described in Table 52 is independent of the Master Abort Mode bit and whether or
not the cycle is exclusive (locked) or not. P64H2 will return all 1s on all data bytes for a read
completion that terminates in either Master Abort or Target Abort on the hub interface. Note that
when a target or master abort is returned on the hub interface, the attached PCI/PCI-X bus is not
locked. This is of special importance to the completion messages of “data parity error”, “byte
count out of range”, “write data parity error”, “device specific”, and reserved/illegal codes. P64H2
must not lock its bus on these errors, even though they are not explicitly master or target aborts on
the PCI-X interface.
Table 52. Split Terminations of Completion Required Cycles to PCI-X
PCI-X Split Termination
Successful
Master Abort
Target Abort
Write Data Parity Error
Byte Count Out Of Range
Write Data Parity Error
Device Specific
Reserved/Illegal
Message
Class Index
Hub Interface
Completion
0
00h Successful
1
00h Master Abort
1
01h Target Abort
1
02h Target Abort
2
00h Target Abort
2
01h Target Abort
2
Others
8Xh Target Abort
Target Abort
Status Register Bits Set
• Master Data Parity Error
(Sec), if encountered
• Received Master Abort (Sec)
• Received Target Abort (Sec)
• Signaled Target Abort (Pri)
• Master Data Parity Error
(Sec)
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
• Master Data Parity Error
(Sec)
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
• Signaled Target Abort (Pri)
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Intel^® 82870P2 P64H2 Datasheet