82870P2P64H2 Datasheet, PDF (31/217 Pages) –

Signal Description
R
2.6
SMBus Interface
Table 11. SMBus Interface Signals
Signal
SDTA
SCLK
Type
Description
I/OD
SMBus Data: SMBus Data Pin. External pull-up required, refer to SMBus 2.0
specification.
I/OD
SMBus Clock: SMBus Clock Pin. External pull-up required, refer to SMBus 2.0
specification.
2.7
Miscellaneous Signals
Table 12. Miscellaneous Signals
Signal
RASERR#
TEST#
RSTIN#
PWROK
TPO
Type
Description
RAS Error: This pin indicates that a Reliability, Availability, and Serviceability
error has been logged. This is an active low signal that is a logical OR of all the
O Reliability, Availability, and Serviceability error events. If one of these errors is
active, the pin is low. If none are active, then the pin is tri-stated. RASERR#
should be tied high to 3.3 V though an 8.2 kΩ pull-up resistor.
I
Intel Test Mode: This signal must be tied high to 3.3 V though an 8.2 kΩ
resistor for normal operation.
Reset In: When asserted, this signal asynchronously resets the P64H2 logic
I and asserts PCIRST# active output from each PCI interface. This signal is
typically connected to the PCIRST# output of the ICH.
I
Power is OK: This signal is used to determine whether the hot plug controller
for a particular interface is in single-slot, dual-slot, or serial mode.
I
Test Point 0: This signal is connect to VCC3.3 through an 8.2 kΩ pull-up
resistor.
Intel^® 82870P2 P64H2 Datasheet
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