82870P2P64H2 Datasheet, PDF (116/217 Pages) –

Functional Description
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Type 0 Accesses to the Intel^® P64H2
The configuration space of the bridge in the P64H2 is accessed by a Type 0 configuration
transaction on the hub interface. The bridge configuration space (as well as the I/OxAPIC and hot
plug configuration spaces) cannot be accessed from PCI. The P64H2 responds to a Type 0
configuration transaction when the following conditions are met by the hub interface address:
• The bus command is a configuration read or configuration write transaction
• Low 2 address bits AD[1:0] must be 00b
• The device number matches one of the P64H2 devices (31–27)
Type 1 to Type 0 Translation
The P64H2 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on
the hub interface and is intended for a device attached directly to the secondary bus. The P64H2
must convert the configuration command to a Type 0 format so that the secondary bus device can
respond to it. This translation is done only for cycles that originate on the hub interface and target
PCI.
The P64H2 translates a Type 1 configuration transaction into a Type 0 transaction under the
following conditions:
• The bus command is a Configuration read or write transaction.
• The low 2 address bits on PxAD [1:0] are 01b.
• The bus number in address field PxAD [23:16] is equal to the value in the secondary bus
number register in P64H2 configuration space.
The resulting Type 0 address to be driven on PCI is shown in Figure 2 Device numbers are
decoded to generate a single 1 in address bits [31:16]. If the device number is greater than 16, all
bits are 0.
Figure 2. Type 1 to Type 0 Translation
31
HI Address
Reserved ’0’
16 15 11 10 7 6
21 0
Dev ID Fnc Register 01
PCI Address
Only one ’1’
0000 Fnc Register 00
Translation_type1-type0
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Intel^® 82870P2 P64H2 Datasheet