82870P2P64H2 Datasheet, PDF (186/217 Pages) –

Electrical Characteristics
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5.1.6.3 PCI Interface DC Characteristics (3.3 V Signaling Environment)
Table 72 summarizes the DC characteristics for 3.3 V signaling.
Table 72. DC Characteristics for PCI 3.3 V Signaling
Symbol
Parameter
Min
Max
Units
Condition
Notes
VCC
VIH
VIL
VIPU
IIL
VOH
VOL
Cin
Cclk
CIDSEL
Supply Voltage
Input High Voltage
Input Low Voltage
Input Pull-up Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
3.135
3.465
V
0.5VCC
VCC +0.5
V
-0.5
0.3VCC
V
0.7VCC
V
±10
µA
0 < Vin < VCC
1
0.9VCC
V
Iout = -500 µA
0.1VCC
V
Iout = 1500 µA
10
pF
5
12
pF
8
pF
4
NOTES:
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
2. Lower capacitance on this input-only pin allows for non-resistive coupling at PxAD[xx].
5.1.6.4 PCI-X Interface DC Characteristics
Table 73 shows the DC characteristics for PCI-X mode.
Table 73. DC Characteristics for PCI-X
Sym
Parameter
Min
Max
Units
Condition
Notes
VCC
VIH
VIL
VIPU
IIL
VOH
VOL
Cin
Cclk
CIDSEL
Supply Voltage
Input High Voltage
Input Low Voltage
Input Pull-up Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
3.135
3.465
V
0.5VCC
VCC +0.5
V
-0.5
0.35VCC
V
0.7VCC
V
±10
µA
0 < Vin < VCC
1
0.9VCC
V
Iout = -500 µA
0.1VCC
V
Iout = 1500 µA
8
PF
2
5
8
PF
8
PF
3
NOTES:
1. Input leakage currents include hi-Z output leakage for all bi-directional buffers with tri-state outputs.
2. Absolute maximum pin capacitance for PCI/PCI-X input except CLK and IDSEL.
3. For conventional PCI only, lower capacitance on this input-only pin allows for non-resistive coupling to
Px_AD[xx]. PCI-X configuration transactions drive the AD bus four clocks before PxFRAME# asserts.
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Intel^® 82870P2 P64H2 Datasheet