82870P2P64H2 Datasheet, PDF (191/217 Pages) –

Electrical Characteristics
R
5.2.1.1 PCI Clock Characteristics
The clock waveform must be delivered to each PCI component in the system. Figure 18 shows the
clock waveform and required measurement points for both 5 V and 3.3 V signaling environments.
Table 78 summarizes the clock specifications.
Figure 18. PCI Clock Waveforms
5 Volt Clock
2.0 V
1.5 V
0.8 V
2.4 V
0.4 V
2 V, p-to-p
(minimum)
3.3 Volt Clock
0.5 Vcc
0.4 Vcc
0.3 Vcc
T_cyc
T_high
0.6 Vcc
T_low
0.2 Vcc
0.4 Vcc, p-to-p
(minimum)
Time_PCI-Clocks
Table 78. PCI Clock Characteristics (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%,
Tcase=0 qC to 105 qC)
66 MHz
33 MHz
Sym
Parameter
Min
Max
Min
Max
Units Notes
Tcyc
PxPCLKO[6:0] cycle time
15
30
30
Infinity
ns 1,3
Thigh
PxPCLKO[6:0] high time
6
11
ns
Tlow
PxPCLKO[6:0] low time
6
11
ns
—
PxPCLKO[6:0] slew rate
1.5
4
1
4
V/ns 2
Fmod
Modulation frequency
30
33
—
—
kHz
Fspread
Frequency spread
-1
0
%
NOTES:
1. In general, all 66 MHz PCI components must work with any clock frequency up to 66 MHz.
PxPCLKO[6:0] requirements vary depending on whether the clock frequency is above 33 MHz.
- Device operational parameters at frequencies at or under 33 MHz will conform to the PCI Local Bus
Specification, Revision 2.2 in Chapter 4. The clock frequency may be changed at any
time during the operation of the system so long as the clock edges remain “clean” (monotonic) and
the minimum cycle and high and low times are not violated. The clock may only be stopped in a low
state. A variance on this specification is allowed for components designed for use on the system
planar only. Refer to PCI Local Bus Specification Revision 2.2 for more information.
- For clock frequencies between 33 MHz and 66 MHz, the clock frequency may not change except
while RSTIN# is asserted or when spread spectrum clocking (SSC) is used to reduce EMI emissions
2. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met
across the minimum peak-to-peak portion of the clock waveform as shown in Figure 19.
3. The minimum clock period must not be violated for any single clock cycle (i.e., accounting for all system
jitter).
Intel^® 82870P2 P64H2 Datasheet
191