82870P2P64H2 Datasheet, PDF (137/217 Pages) –

Functional Description
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Figure 3. Serial Input 6-slot Stutter Mode
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4.3.1.4
Serial Input Stream
The serial input stream constantly runs once the P64H2 is out of reset (RSTIN# deasserted). Under
normal operation, the input stream consists of a repeating series of 8 bytes of serial data. Note,
however, that because of stutter logic, some of these serial input bits are not shifted out of the
external shift registers (see previous section). It is possible to extend the serial input stream length
to 16 bytes through the use of the Serial Input Register.
The first 4-bytes of the serial input stream are interrupting inputs. The remaining 4-bytes are non-
interrupting inputs. Because only six-slots are supported by the P64H2, only 24 of the 32
interrupting inputs are available. Each slot has six inputs. The first group of inputs function as the
slot switches. The second group are slot power fault indicators. The remaining 12 interrupt-
capable inputs are the slot card present bits.
A change on any of the switch inputs initiates a 15 ms glitch filter timer. If a change is detected on
any slot switch input, the switch input is re-scanned 32 times within a 15 ms time interval. If the
switches remain stable for 32 samples, the HMIC is updated to reflect the change in state. If any
switch is still changing state, the glitch filter counter is cleared and the sequence restarts. If not
masked, a switch change interrupt is also generated after the HMIC changes state. The interrupt
function can be masked using the HMIR, but the HMIC always reflects a state change.
A change on any of the non-switch inputs causes an immediate change in the state of the HMIC.
An interrupt is also generated unless masked in the HMIR. After a non-switch input changes state,
further updates to all other non-switch bits of the HMIC is inhibited for an 8 ms de-bounce period.
This prevents a rapid succession of interrupts from being generated before software has time to
react.
In summary, an interrupt is generated and the interrupt pending bit is set in the MCNF Register in
memory space if all of the following are true:
• An interrupt is not already pending, and
• A switch input changes state and remains in its new state at the end of the glitch filter time
period, or a non-switch interrupting input has changed state at the beginning of the de-bounce
period, and
• The interrupt mask bit for that input is cleared (logic 0).
If an interrupt bit changes state in the HMIC and is not masked, the value is frozen in then HMIC
until acknowledged by writing 1 to this bit position. In the case of an unmasked non-switch input
already causing an interrupt to be generated, if the de-bounce timer expires and the interrupt has
Intel^® 82870P2 P64H2 Datasheet
137