82870P2P64H2 Datasheet, PDF (197/217 Pages) –

Electrical Characteristics
R
5.2.2.3 P64H2 Clock Timings
1.8V to CLK66 Sequencing Requirement –
1.8V needs to be valid before CLK66 begins to toggle. This can be guaranteed by gating the
CK408 clocks using a power good signal from the 1.8V regulator. Current designs will need to
implement the BIOS workaround defined in the P64H2 BIOS Spec Update. New board designs
should adhere to the hardware power sequencing requirement outlined in the next version of the
Intel Xeon Processor with 512K L2 Cache and Intel E7500 and Intel E7501 Chipset Compatible
Platform Design Guide v1.9 and the Intel Xeon Processor with 512 KB L2 Cache and Intel E7500
Chipset Platform Design Guide Update v1.1.
Failure to meet these requirements may result in:
• The PLL not locking
• Erratic behavior of PCI/PCI-X output clocks (i.e. runt pulses, multiple pulses)
• Reads to the P64H2 and PCI/PCI-X failing
• PCI/PCI-X cards not enumerating correctly
Failure to meet this requirement will NOT result in data corruption or an unreliable system. If this
issue is encountered, the system will fail to boot.
Table 83. P64H2 Clock Timings (HI_VREF = 5 V + 5%, VCC = 3.3 V + 5%, Tcase=0qC to 105qC)
Symbol
CLK66
Tperiod
Thigh
Tlow
Trise
Tfall
—
—
CLK200
Tperiod
Trise
Tfall
—
—
Tccjitter
—
—
—
Parameter
CLK period
CLK high time
CLK low time
CLK rise time
CLK fall time
Rising edge rate
Falling edge rate
Average Period
Rise time across 600 mV
Fall time across 600 mV
Rise/Fall Matching
Cross point at 1 V
Cycle to Cycle jitter
Duty Cycle
Maximum voltage allowed at input
Minimum voltage allowed at input
Min
Max
Units
Notes
15.0
15.3
ns
1,2
4.95
N/A
ns
3
4.55
N/A
ns
4
0.5
2.0
ns
5
0.5
2.0
ns
5
1.0
4.0
V/ns 5
1.0
4.0
V/ns 5
5.0
5.2
ns
6
300
600
ps
7,8
300
600
ps
7,8
20%
7,9
0.51
0.76
V
200
ps
45
55
%
1.45
V
-200
mV
Intel^® 82870P2 P64H2 Datasheet
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