82870P2P64H2 Datasheet, PDF (146/217 Pages) –

Functional Description
R
Table 43. Power Down Timings (CBL Mode)
Timing Event
BUSEN# Deassertion to RESET# Assertion
RESET# Assertion to CLKEN# De-assertion
CLKEN# Deassertion to PWREN De-assertion
NOTE: Arbitration latency affects the minimum time.
Minimum¹
330
5.468
5.438
Maximum
330
14.445
14.415
Units
ns
us
us
4.3.1.7
Arbitration
The hot plug controller requests a hold from the P64H2 arbiter at various stages of enabling or
disabling slots. This is performed to prevent glitches that might occur while switching bus signals
from affecting the rest of the system. When a request to the P64H2 arbiter occurs from the hot
plug function, the P64H2 arbitrates to hot plug at the next convenient opportunity and suppresses
grants to external masters. When the bus is idle, hot plug is granted and it performs its operations.
4.3.1.8 Power-on and Reset Initialization
All registers in the P64H2 hot plug controller are reset by the primary bus reset pin (RSTIN#). The
secondary bus reset will reset most of the controller’s registers, except for the few listed in
Table 44.
Table 44. Registers Not Reset with a Secondary Bus Reset
Memory Registers
General Purpose Timer Register (offset 00h)
Slot Enable Register (offset 01h)
LED Control Register (offset 04h)
HMIC Register (offset 08h)
HMIR Register (offset 0Ch)
SIR Register (offset 10h)
GPO Register (offset 13h)
HMIN Register (offset 14h)
Slot Power Register (offset 2Dh)
Configuration Registers
Subsystem ID Register (offset 2Ch)
MCNF Register (offset 42h); CBL control bit (bit 1).
On a RSTIN# assertion, the slot-specific output controls are set to the following states:
• RESET# is asserted.
• BUSEN# is deasserted (disconnected from the bus).
• CLKEN# is deasserted (PCI clock disconnected from the bus).
• PWREN is deasserted (slot power is removed).
• All green and amber LED outputs are set to OFF.
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Intel^® 82870P2 P64H2 Datasheet