82870P2P64H2 Datasheet, PDF (142/217 Pages) –

Functional Description
R
Shift Register Assignments
GPO[7:0] are shifted out before the reset enables. This is done to support a system that does not
need the GPOA outputs. For a system using less than six slots, stutter logic can be utilized to
reduce the number of output shift registers and latches. Serial mode output shifting is shown in
Table 39.
Table 39. Serial Mode Output Shift-Out SR Bit Order
SR Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Function
gpo7
gpo6
gpo5
gpo4
gpo3
gpo2
gpo1
gpo0
reset# 1
reset# 2
reset# 3
reset# 4
reset# 5
Reset# 6
grnled 1
SR Bit
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Function
ambled 1
grnled 2
ambled 2
grnled 3
ambled 3
grnled 4
ambled 4
grnled 5
ambled 5
grnled 6
ambled 6
busen 1
busen 2
busen 3
busen 4
SR Bit
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Function
busen 5
busen 6
clken 1
clken 2
clken 3
clken 4
clken 5
clken 6
pwren 1
pwren 2
pwren 3
pwren 4
pwren 5
pwren 6
LEDs
Each slot has a green and amber LED for communicating slot status to the user. Each LED has 4
states (ON, OFF, BLINK PHASE A, and BLINK PHASE B) controlled by the LED Control
Register (LEDC).
A single timer controls blinking for all LEDs and is hardwired to 1 Hz at a 50% duty cycle,
derived from the PCI clock frequency. Phase A is on for the first half of each one-second period
and phase B is on for the second half.
When a switch for a slot indicates that the slot has been opened, both LEDs are turned off by the
P64H2. The LEDs can later be programmed by software to turn on or blink the LEDs, whether or
not the slot is open. It is the responsibility of software to insure that the LEDs never indicate that a
slot is powered down when the slot has power.
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Intel^® 82870P2 P64H2 Datasheet