82870P2P64H2 Datasheet, PDF (93/217 Pages) –

Register Description
R
3.3.2.13
EMR—Extended Hot Plug Miscellaneous Register
Offset:
32–33h
Default Value: 00h
Attribute:
Size:
R/W
16 bits
This register contains additional miscellaneous functions related to the hot plug controller.
Bits
Description
15:3 Reserved
Arbiter Timeout SERR Enable (ATSE).
0 = Disable. (default)
2
1 = Causes a SERR to be generated when an arbiter timeout occurs. This event is indicated in
both the Arbiter Timer Timeout (ATT) bit in the MCNF Register in memory space and Arbiter
Timeout SERR Status (ATS) bit in the SERR Status Register in PCI configuration space.
Arbiter Timeout Interrupt Enable (ATIE).
1
0 = Disable. (default)
1 = Causes an interrupt to be generated when an arbiter timeout occurs. Writing 1 to the Arbiter
Timer Timeout (ATT) bit (MCNF Register in memory space) clears this interrupt.
Inhibit Arbiter Timeouts (IAT).
0 = Power sequencing state machine starts a timer when it requests the bus (bus requests
occur for most phases of power sequencing). If the arbiter takes too long to return bus grant
to the Hot plug logic, an arbiter timeout occurs and the power sequence phase executes
0
without bus ownership. (default)
1 = Causes the power sequence logic to wait for the bus grant forever. The auto-power down
feature (opening a slot switch) does NOT successfully cause the slot to be powered off,
which presents a potential risk to a system whose bus is hung. Even though this bit is set,
an SERR or interrupt can be generated when an arbiter timeout would have occurred (see
bits 17 and 18).
Intel^® 82870P2 P64H2 Datasheet
93