82870P2P64H2 Datasheet, PDF (175/217 Pages) –

Functional Description
R
4.9
Reliability, Availability, and Serviceability (RAS)
It is important for the P64H2 to log error information in server environments, such that software
has the ability to recover from the error. Errors fall into two classes:
• Integrity errors on busses (PCI/ hub interface)
• Soft errors inside of the component (in the case of the P64H2, the data RAMs).
When logging the error, it is important that the first one be logged. Chances are, when you receive
an error, you are about to receive multiple errors; therefore, it is important to know where the error
chain began. Thus, the logic associated with logging errors will have a “lock down” feature to it.
Once an error is detected, it is logged and no other errors will be logged until the first error is
cleared.
RAS logging will be simplified into four rules, and two new terms. The new terms are:
• Context Data: The address/data of the cycle that caused the error. For example, on a cycle
that is split, the context address is the address of the cycle on the original request, not on the
completion.
• Live Data:The value of the pins (address, data, byte enables, header) of the error.
The rules are:
• Cycle Errors: Target Abort and Master Abort are cycle errors. In these types of errors, the
context data is stored along with the error indication. This is stored as opposed to live data
because there is nothing fundamentally wrong with the live data – it is the context data that
resulted in the error.
• Address Parity Errors: Live data is stored in these types of errors, because the P64H2 does
not have enough information as to what the intended address was supposed to be, and the live
data is needed to decode the parity error.
• Data Parity Errors: Live data is stored for the erroneous data, and context address is stored
for the address. The live data is needed to decode the parity error, and the context address is
needed in case software can recover.
• The hub interface stores errors only as a receiver, where PCI stores errors as a receiver and a
generator. Hub interface errors can be simplified because the same RAS functionality in the
P64H2 is also in the MCH, and the burden can be shared, while PCI cards do not have the
same level of RAS so the P64H2 must keep more information around.
The RAS feature bits are sticky through reset. Therefore, the registers at offset 60h of each hub
interface to PCI bridge (device 31 and 30), bits 5:0 and 13:8, which signify RAS events, are not
cleared. BIOS must clear these at system power up.
Intel^® 82870P2 P64H2 Datasheet
175