82870P2P64H2 Datasheet, PDF (88/217 Pages) –

Register Description
R
3.3.2.5
HMIC—Hot Plug Interrupt Input and Clear Register
Offset:
08–0Bh
Default Value: 00h
Attribute:
Size:
R/WC
32 bits
This register is used to read the current state of the general interrupt inputs when no interrupt is
pending. When one of the below inputs changes state (either high-to-low or low-to-high) and that
bit is not masked in the HMIR Register, an interrupt is generated and the state of that interrupting
input is latched in this register. The value in the register then represents the latched state of that
interrupting input. A write of 1 to this register in the bit positions of any bits that have changed
clears the interrupt and allows the register to be updated with the current state of that input signal.
Note: Unimplemented slots may have interrupt bits set in these registers; therefore, software should mask
the corresponding locations in the mask register.
Note: The reset value of this register is 0; however, this may change after the first scan in sequence
which may be before software is able to access this register.
Note: The bits that pertain to disabled slots (not enabled by HPx_SLOT[2:0] power on straps) reflect the
value of the last enabled slot. For example, if slots 3, 4, 5, 6 are disabled, their corresponding bits
in this register will match the bit value for slot 2.
Bits
Description
31:30
29:24
23:22
21:16
15:14
13:8
7:6
5:0
Reserved
PRSNT1# (SP1). Present Signal 1 from the PCI slot connector. This signal is the latched state of
the PRSNT1# pin when the pin changes state and causes an interrupt. When 0, the slot present
bit is active (0). Bit 29 represents slot F, bit 28 represents slot E, etc. until bit 24, which
represents slot A.
Reserved
PRSNT2# (SP2). Present Signal 2 from the PCI slot connector. This signal is the latched state of
the PRSNT2# pin when the pin changes state and causes an interrupt. When 0, the slot present
bit is active (0). Bit 21 represents slot F, bit 20 represents slot E, etc. until bit 16, which
represents slot A.
Reserved
FAULT# (SF). Power Fault from the motherboard. This signal is the latched state of the FAULT#
pin when the pin changes state and causes an interrupt. When 0, the power fault is active (0).
Bit 13 represents slot F, bit 12 represents slot E, etc. until bit 8, which represents slot A.
Reserved
Switch (SS). Slot Switch from the chassis. This signal is the latched state of the switch pin when
the pin changes state and causes an interrupt. When 0, the slot switch is closed (0). Bit 5
represents slot F, bit 4 represents slot E, etc. until bit 0, which represents slot A.
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Intel^® 82870P2 P64H2 Datasheet