82870P2P64H2 Datasheet, PDF (43/217 Pages) –

Register Description
R
3.2.10
BNUM—Bus Number Register (D29,31: F0)
Offset:
18–1Ah
Default Value: 000000h
Attribute:
Size:
R/W
24 bits
This contains the primary, secondary, and maximum subordinate bus number registers.
Bits
23:16
15:08
7:0
Description
Subordinate Bus Number (SBBN). This field indicates the highest PCI bus number below this
bridge. Any type 1 configuration cycle on the hub interface whose bus number is greater than the
secondary bus number and less than or equal to the subordinate bus number will be run as a
type 1 configuration cycle on the PCI bus.
Secondary Bus Number (SCBN). This field indicates the bus number of PCI to which the
secondary interface is connected. Any type 1 configuration cycle matching this bus number will
be translated to a type 0 configuration cycle and run on the PCI bus.
Primary Bus Number (PBN). This field indicates the bus number of the hub interface. Any type
1 configuration cycle with a bus number less than this number will not be accepted by this portion
of the P64H2 (in other words, it still may match the other bridge).
3.2.11
SMLT—Secondary Master Latency Timer (D29,31: F0)
Offset:
1Bh
Default Value: 00h
Attribute:
Size:
R/W
8 bits
This timer controls the amount of time that the P64H2 will continue to burst data on its secondary
interface. The counter starts counting down from the assertion of PxFRAME#. If the grant is
removed, then the expiration of this counter will result in the deassertion of PxFRAME#. If the
grant has not been removed, then the P64H2 may continue ownership of the bus. Secondary
latency timer’s default value should be 64 in PCI-X mode (Section 8.6.1 of the PCI-X Addendum
to the PCI Local Bus Specification, Revision 1.0).
Bits
Description
Secondary Latency Timer (TV). This 5-bit value indicates the number of PCI clocks, in 8-clock
7:3 increments, that the P64H2 remains as a master of the PCI bus if another master is requesting
use of the PCI bus.
2:0 Reserved
Intel^® 82870P2 P64H2 Datasheet
43