82870P2P64H2 Datasheet, PDF (171/217 Pages) –

Functional Description
R
4.8
System Setup
4.8.1 Clocking
In addition to 33 MHz and 66MHz PCI output clocking, the P64H2 requires 100 MHz and
133 MHz outputs to support PCI-X. Table 58 shows the P64H2 clock domains.
Table 58. P64H2 Clocking
Clock Domain Frequency
Hub Interface
66 MHz
Hub Interface
Data
266 MHz /
533 MHz
PCI
133/100/66/
33 MHz
APIC
16–33 MHz
SMBus
KHz
Source
Main Clock
Generator
Internal
Internal
External
Source
Synchronous
Usage
Hub interface core
Hub interface data transfers. Not externally
visible. Internal only to hub interface devices.
Generated by internal PLL from the hub interface
clock.
PCI Bus. These only go to external PCI Bus.
Used for the Intel® P64H2 interrupt messages.
Typically will be 16.6667 MHz, but can be 33MHz
for FRC mode. Only used for P6 FSB platforms.
Tied high otherwise.
This pin is controlled by the driver of the SMBus
interface, and will run between 10 and 100 kHz.
The PCI/PCI-X input clock for each interface, PxPCLKI, can be considered to have a synchronous
relationship to the hub interface input clock (CLK66) provided the following three conditions are
met.
• The PxPCLKI input is connected to the PxPCLKO6 PCI clock output, and
• The PxPCLKI input meets the T_skew (min) and T_skew (max) timing relative to CLK66.
• The PxPCLKI is running at 33 or 66 MHz.
If the above three conditions are met for an interface, configuration offset E0h bit 4 can be set to a
1 and the PCI clock and the hub interface clock will be treated as synchronous clocks to reduce
data latency.
If the input PxPCLKI is driven from an external clock driver and not PxPCLKO0, or if T_skew (min)
and T_skew (max) are not met, or if the PCI-X bus frequency is 100 MHz or 133 MHz, BIOS should
leave configuration offset E0h bit 4 at its reset value of 0 and the clocks will be considered
asynchronous.
Intel^® 82870P2 P64H2 Datasheet
171