82870P2P64H2 Datasheet, PDF (143/217 Pages) –

Functional Description
R
GPO
General-purpose outputs are used for non-slot specific system functions. These outputs are part of
the serial output chain but are not affected by the number of slots detected on HP_SLOT[2:0].
4.3.1.6
Power Sequencing
Each slot uses 4 control signals to enable and disable PCI-X cards: PWREN, CLKEN#, BUSEN#
and RESET#. Power sequencing can be performed in one of two ways, as selected by the CBLE
(Connect Bus Last Enable) bit in the MCNF Register in PCI configuration space. If CBLE is
cleared, the PCI bus is connected before the slot reset is deasserted. If CBLE is set, the PCI bus is
connected after the slot reset has been deasserted.
Any slot can be individually powered on by setting the appropriate bit of the Slot Power Enable
register. These bits affect only the state of the PWREN pin for that slot; they do not affect the
clock, connection to the bus, or slot reset.
Power Up (CBF Mode)
When a slot is to be turned on in CBF mode, the outputs are updated in the following sequence:
2. Assert PWREN, but keep BUSEN# and CLKEN# deasserted and RESET# asserted. Shift the
new pattern to the shift registers.
3. Clock the parallel latch HP_SOL. The new values for LEDs are clocked out at this point as
well.
4. With PWREN asserted, assert CLKEN# bit but leave BUSEN# deasserted and RESET#
asserted. Shift the new pattern to the shift registers.
5. Wait for 500 ms for power to stabilize.
6. Arbitrate for an idle bus, and clock the parallel latch HP_SOL.
7. With PWREN and CLKEN# asserted, assert BUSEN# to connect the bus, and deassert
RESET# Shift the new pattern to the shift registers.
8. Wait for 500 ms for expansion card clocks to stabilize.
9. Arbitrate for an idle bus time, and clock the parallel latch HP_SOL. However, since
HP_SOLR is not clocked, the RESET# pin remains asserted to the device.
10. Wait for 330 ns.
11. Clock the parallel latch HP_SOLR, to negate reset.
Table 40. Power Up Timings (CBF Mode)
Timing Event
PWREN Assertion to CLKEN# Assertion
CLKEN# Assertion to BUSEN# Assertion
BUSEN# Assertion to RESET# Deassertion
Minimum¹
500
500
330
Maximum
505
505
330
Units
ms
ms
ns
NOTES:
1. Arbitration latency affects the minimum time.
Intel^® 82870P2 P64H2 Datasheet
143