82870P2P64H2 Datasheet, PDF (73/217 Pages) –

Register Description
R
3.3.1.6
3.3.1.7
3.3.1.8
CC—Class Code Register (Device 31)
Offset:
09–0Bh
Default Value: 840h
Attribute:
Size:
RO
24 bits
This register contains the base class, sub-class, and programming interface codes.
Bits
Description
23:16
15:8
7:0
Base Class Code (BCC).
08h = Generic system peripheral class device.
Sub Class Code (SCC).
04h = Generic PCI hot plug controller.
Programming Interface (PIF). The hot plug controller has no programming interface.
MBAR—Memory Base Register (Device 31)
Offset:
10–13h
Default Value: 0000000Ch
Attribute:
Size:
R/W, RO
32 bits
This register is used by the hot plug logic to request a 256-byte prefetchable memory space that
can be located anywhere in the 64-bit address space. Once programmed, the memory registers will
respond at this address. Bits 31:4 will be the lower 32-bits of the address. Offset 14h contains the
upper 32-bits of the base address.
Bits
Description
31:8 Base Address (BAR)—R/W. This field can be any value.
7:4
Memory Space Size (SIZE)—RO. Hardwired to 0; indicates 256-bytes of address space is
requested.
3
Prefetchable (PF)—RO. Hardwired to 1; indicates that the memory space is prefetchable.
2:1
Memory location (LOC)—RO. Hardwired to 10; the memory space can be located anywhere in
the 64-bit address space.
0
Indicator (IND)—RO. Hardwired to 0; indicates that the BAR is for memory space.
MBARU—Memory Base Address (Upper 32-bits) Register (Device 31)
Offset:
14–17h
Default Value: 00000000h
Attribute:
Size:
R/W
32 bits
Bits
Description
31:0 Upper 32-bits of Address (ADDR): These bits determine bits 63:32 of the base address.
Intel^® 82870P2 P64H2 Datasheet
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