82870P2P64H2 Datasheet, PDF (94/217 Pages) –

Register Description
R
3.4
I/OxAPIC Interrupt Controller Registers
The P64H2 contains two I/O APIC controllers (I/OxAPIC where x is either A or B), both reside
on the primary bus. The intended use of these controllers is to have the interrupts from PCI bus A
connected to the interrupt controller on device 28, and have the interrupts on PCI bus B connected
to the interrupt controller on device 30. The I/OxAPIC controllers contain PCI Configuration
registers (See Section 3.4.1) and memory space registers (see Sections 3.4.2 and 3.4.3).
3.4.1 PCI Configuration Space Registers (Device 28 and 30)
Table 18. I/OxAPIC PCI Configuration Space Register Map
Address
Offset
00–01h
02–03h
04–05h
Symbol
VID
DID
PCICMD
Register Name
Vendor ID Register
Device ID Register
PCI Device Command Register
06–07h
PCISTS PCI Device Status Register
08h
09–0Bh
0C–0Fh
10–13h
14–2Bh
2C–2Fh
30–33h
34h
35–3Fh
40–41h
42–4Fh
50–51h
52h
53h
RID
CC
HDR
MBAR
—
SS
—
CAP_PTR
—
ABAR
—
XID
XCR
—
Revision ID Register
Class Code Register
Header
Memory Base Register
Reserved
Subsystem Identifiers
Reserved
Capabilities Pointer
Reserved
Alternate Base Address Register
Reserved
PCI-X Identifiers
PCI-X Command Register
Reserved
54–57h
XSR
PCI-X Status Register
80h
Alias of memory space registers at 00h, 10h, 20h, and 40h
Default
8086h
1461h
0000h
0030h
11h
080020h
00000000h
00000000h
—
00000000h
—
50h
—
0000h
—
0007h
00h
—
000300F0h
(bus A)
000300E0h
(bus B)
Attribute
RO
RO
R/W, RO
R/W, RO,
R/WC
RO
RO
RO
R/W
—
R/W
—
RO
—
R/W
—
RO
RO
—
RO
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Intel^® 82870P2 P64H2 Datasheet