82870P2P64H2 Datasheet, PDF (50/217 Pages) –

Register Description
R
Bits
Description
VGA Enable (VGAE)—R/W. This bit modifies the P64H2’s response to VGA compatible address.
0 = When the bit is 0, memory and I/O addresses on the secondary interface between the
ranges shown below will be forwarded to the hub interface.
1 = P64H2 forwards the following transactions from the hub interface to PCI regardless of the
value of the I/O Base and Limit Address Registers. The transactions are qualified by the
3
Memory Enable bit and I/O Enable bit in the PCI Primary Device Command Register
(offset 04–05h).
Memory addresses: 000A0000h–000BFFFFh
I/O addresses:
3B0h–3BBh and 3C0h-3DFh. For the I/O addresses, bits [63:16] of
the address must be 0, and bits [15:10] of the address are ignored
(i.e., aliased).
ISA Enable (IE)—R/W. This bit modifies the response by the bridge to ISA I/O addresses. This
only applies to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in
the first 64 KB of PCI I/O space.
2
0 = Disable.
1 = Enable. The bridge will block any forwarding from primary to secondary of I/O transactions
addressing the last 768 bytes in each 1 KB block (offsets 100h to 3FFh). This bit has no
effect on transfers originating on the secondary bus as the P64H2 does not forward I/O
transactions across the bridge.
SERR# Enable (SE)—R/W. This bit controls the forwarding of secondary interface SERR#
assertions on the primary interface.
0 = Disable
1 = Enable. P64H2 will send a hub interface DO_SERR special cycle when all of the following
1
are true:
• SERR# is asserted on the secondary interface.
• This bit is set
• The SERR# Enable bit in the PCI Primary Device Command Register (offset 04–05h) is
set.
Parity Error Response Enable (PERE)—R/W. This bit control’s the P64H2’s response to
address and data parity errors on the secondary interface.
0
0 = Disable. The bridge must ignore any parity errors that it detects and continue normal
operation. The P64H2 must generate parity even if parity error reporting is disabled.
1 = Enable. Parity errors reported on the secondary interface.
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Intel^® 82870P2 P64H2 Datasheet