82870P2P64H2 Datasheet, PDF (144/217 Pages) –

Functional Description
R
Power Down (CBF Mode)
When a slot is to be turned off in the CBF mode, the outputs are updated in the following
sequence:
1. Assert RESET# and negate the BUSEN# but leave CLKEN# asserted and PWREN asserted.
Shift the new pattern to the shift registers.
2. Arbitrate for an idle bus and clock the parallel latch HP_SOLR, which asserts RESET# to the
card. Since HP_SOL is not clocked, BUSEN# stays asserted.
3. Wait 330 ns and clock the parallel latch HP_SOL to assert BUSEN#.
4. With RESET# asserted and BUSEN# deasserted, deassert CLKEN# but leave PWREN
asserted. Shift the new pattern to the shift registers.
5. Arbitrate for an idle bus, and clock the parallel latch HP_SOL.
6. With RESET# asserted and BUSEN# and CLKEN# deasserted, deassert PWREN. Shift the
new pattern to the shift registers.
7. Clock the parallel latch HP_SOL.
Table 41. Power Down Timings (CBF Mode)
Timing Event
RESET# Assertion to BUSEN# Deassertion
BUSEN# De-assertion to CLKEN# Deassertion
CLKEN# De-assertion to PWEREN Deassertion
NOTES:
1. Arbitration latency affects the minimum time.
Minimum¹
330
5.468
5.438
Maximum
330
14.445
14.415
Units
ns
us
us
144
Intel^® 82870P2 P64H2 Datasheet