82870P2P64H2 Datasheet, PDF (160/217 Pages) –

Functional Description
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4.6
I/OxAPIC Interrupt Controller (Device 30 and 28)
The P64H2 contains two I/OxAPIC controllers (where x=A or B for PCI Bus A or PCI Bus B),
both of which reside on the primary bus. The intended use of these controllers is to have the
interrupts from PCI bus A connected to the interrupt controller on device 28, and have the
interrupts on PCI bus B connected to the interrupt controller on device 30.
4.6.1 Interrupt Insertion
Interrupts can be delivered to the P64H2 in one of two fashions – either as a pin or a directed
memory write (MSI).
4.6.1.1
Pin Interrupts
Interrupts delivered by a pin can be either in level or edge mode, and may be either active high or
active low. Since this I/OxAPIC is connected to a PCI bus, it’s most likely configuration will be as
active low level, which will match the PCI pin polarity and functionality.
Each pin is collected by the P64H2, synchronized into the 66 MHz clock domain, and scheduled
for delivery if it is unmasked.
Note:
The P64H2 has 16 interrupt pins per PCI segment. These pins are connected to redirection table
entries 15 – 0. The hot plug controller is hard-wired to redirection table entry 23 of the APIC on
device 28 (PCI bus A). All other interrupts are only addressable through MSI commands. The
unused pins on the I/OxAPIC unit must be connected to VCC3.3 to ensure the boot interrupt
works correctly.
4.6.1.2
Message Signaled Interrupts (MSI)
In this mode of operation, PCI devices are given a write path directly to the pin assertion register
(memory offset 20h) in the I/OxAPIC that causes the interrupt. Upon accepting the write, the
P64H2 will send the interrupt message to the processor (if the interrupt is unmasked). Interrupts
associated with the PCI Message-based interrupt method must be in edge-triggered mode, but the
level setting (active high or active low) is irrelevant.
4.6.2
4.6.2.1
Interrupt Delivery
The P64H2 I/OxAPIC can deliver interrupts to the processor through the system bus (via the hub
interface).
Front-Side Interrupt Delivery
Interrupt delivery is performed by the P64H2 writing (via the hub interface) directly to a memory
location located in a processor. Software enables the mode by setting the DT bit in the ID
Register.
When operating in this mode, when the IRR bit is set for an interrupt, the P64H2 will perform a
memory write on the hub interface, as seen in Table 55 and Table 56.
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Intel^® 82870P2 P64H2 Datasheet