82870P2P64H2 Datasheet, PDF (96/217 Pages) –

Register Description
R
3.4.1.3
PCICMD—PCI Device Command Register (D28,30: F0)
Offset:
04–05h
Default Value: 0000h
Attribute:
Size:
R/W, RO
16 bits
This register controls how the device behaves.
Bits
Description
15:10
9
8
7
6
5
4
3
2
1
0
Reserved
Fast Back-to-Back Enable (FBE)—RO. Hardwired to 0; Reserved
SERR# Enable (SEE)—R/W. This bit controls the enable for the DO_SERR special cycle on the
hub interface.
0 = Disable special cycle. (default)
1 = Enable special cycle.
Wait Cycle Control (WCC)—RO. Hardwired to 0; Reserved
Parity Error Response Enable (PERE)—R/W. This bit enables checking of parity.
0 = Disable (default)
1 = Enable
VGA Palette Snoop Enable (VGA_PSE)—RO. Hardwired to 0; Reserved
Memory Write and Invalidate Enable (MWIE)—RO. Hardwired to 0; Reserved
Special Cycle Enable (SCE)—RO. Hardwired to 0; Reserved
Bus Master Enable (BME)—R/W. This bit controls the I/OxAPIC’s ability to act as a master on
the hub interface when forwarding system bus interrupt messages.
0 = Disable (default)
1 = Enable
Memory Space Enable (MSE)—R/W. This bit controls the I/OxAPIC’s response as a target to
memory accesses that address the I/OxAPIC.
0 = Disable (default)
1 = Enable
I/O Space Enable (IOSE)—RO. Hardwired to 0; Reserved
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Intel^® 82870P2 P64H2 Datasheet