82870P2P64H2 Datasheet, PDF (163/217 Pages) –

Functional Description
R
4.7
SMBus Interface
The SMBus interface does not have any PCI configuration registers. The SMBus address is set
upon PWROK by sampling PAGNT[5:4] and PBGNT[5:4]. When the pins are sampled, the
resulting P64H2 address will be as shown in Table 57.
Table 57. SMBus Address Configuration
Bit
Value
7
1
6
1
5
PAGNT5
4
0
3
PAGNT4
2
PBGNT5
1
PBGNT4
4.7.1
The SMBus controller has access to all internal registers. The generation of cycles on the hub
interface or PCI is not supported transactions, and undefined results may occur if they are
attempted. It can perform reads and writes from all registers through the particular interface’s
configuration space. Hot plug and I/OxAPIC memory spaces are accessible through their
respective configuration spaces.
SMBus Signaling
The SMBus interface includes a pair of signals: SCL (clock) and SDA (serial data). SCL provides
the timing mechanism for data transfers. The SMBus master always drives SCL. SDA carries the
data as driven by the sending device (sender), which can be the initiator or the target.
An initiator starts a transfer over the SMBus when it is free. Details of how initiators arbitrate are
not described here. The current initiator communicates to the desired target through a unique
seven-bit address to the target, sent MSb to LSb. All devices monitor the generated address after
detecting the start condition. Once seven address bits are received, all targets compare the received
address with their own and the target slave finds a match.
The next data bit from the initiator indicates the transfer direction. A value of 1 indicates that the
target needs to transfer data to the initiator (read). Data transfers over SMBus are performed in
8-bit chunks. Data is transferred from MSb to LSb.
Intel^® 82870P2 P64H2 Datasheet
163