82870P2P64H2 Datasheet, PDF (59/217 Pages) –

Register Description
R
3.2.31
RAS_DI—RAS Data Integrity Codes Register (D29,31: F0)
Offset:
64–66h
Default Value: xxxxxxh
Attribute:
Size:
RO
24 bits
This register contains the ECC and parity bit information from the failed cycle.
Bits
Description
23:19
18
17
16
15:0
Reserved
PCI-X Attribute Parity (PP). This bit represents the parity detected in the attribute phase of a
request and completion. When the Intel® P64H2 is driving, it is the value driven. When the
P64H2 is receiving, it is the value captured.
PCI Address High (PAH). This bit represents the parity detected in the second phase (upper
32-bits) of a dual address cycle. It is forced to 0 if the address was a single address cycle. When
the P64H2 is driving, it is the value driven. When the P64H2 is receiving, it is the value captured.
PCI Address Low (PAL). For PCI-X requests and all PCI cycles, this bit represents the parity
detected in the first phase (lower 32-bits) of a dual address cycle, or just the address of a regular
address cycle. For PCI-X completions, this bit represents the first clock (requester attributes)
driven in the completion cycle. When the P64H2 is driving, it is the value driven. When the
P64H2 is receiving, it is the value captured.
Hub Interface Data Integrity (HDI). This field is only visible from device 31.This field is only
valid if the AEHS, AEHM, DEHM, DEHS, or DEBI bits are set in the RAS_STS Register (60h).
This field contains the captures the hub interface ECC or parity code of the failure. Only bit '0' is
used if in parity mode for Hub Interface2.0.
If the type of error is an address error, then this is the code for the header that failed. If the type
of error is a data error, then this is the code for the data that failed.
3.2.32
RAS_PH—RAS PCI Header Register (D29,31: F0)
Offset:
6C–6Dh
Default Value: xxxxh
Attribute:
Size:
RO
16 bits
This register contains the PCI header information from a PCI failure. The bits in this register are
only valid if the AEP, DEP, PRTA, PRMA, or DEBO bits are set in the RAS_STS Register (60h).
Bits
Description
15:12
11:8
7:0
Reserved
PCI Command (PCMD). This field logs the command of the PCI bus when there is a failure.
PCI Byte Enables (PBE). This field contains the 8-byte enables, which are part of the error. If
the cycle was only in 32-bit mode, then only the low 4 bits are valid.
Intel^® 82870P2 P64H2 Datasheet
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