82870P2P64H2 Datasheet, PDF (173/217 Pages) –

Functional Description
R
4.8.2.2 RSTIN#
This reset also occurs upon a PowerOK reset. This reset causes the P64H2 to set the initial
frequency for each PCI bus (based on Table 59).
Table 59. Determining PCI/PCI-X Bus Frequency
Hot Plug Exists?¹
Px_133EN
PxM66EN
PxPCIXCAP
Yes
Don’t Care
Don’t Care
Don’t Care
Don’t Care
0
0
Don’t Care
1
0
No
Don’t Care
Don’t Care
Low
0
Don’t Care
1
1
Don’t Care
1
NOTES:
1. See Section 4.8.2.3 to see how hot plug existence is determined.
Bus Mode
PCI 33
PCI 33
PCI 66
PCI-X 66
PCI-X 100
PCI-X 133
4.8.2.3 PowerOK
The primary purpose of this reset is to determine the hot plug mode. While this reset is active
(low), the hot plug mode is unknown, and could be single-slot with no isolation logic. To avoid
damage to the system, each PCI bus is driven to ground until PowerOK goes inactive, sampling
HPx_SLOT[2:0].
It may take the P64H2 up to 128 ms after primary reset deassertion and up to 2 ms after secondary
bus reset deassertion for the PCI buffers to be fully compensated. System BIOS timings must
guarantee that no PCI cycles are attempted on the P64H2 PCI bus during these times.
When this pin goes inactive, HPx_SLOT[2:0] are sampled to determine the hot plug mode and
final bus state (see Table 60).
Table 60. Hot Plug Mode and Final Bus State
HPx_SLOT[2:0]
000
001
010–111
Hot Plug Exists?
No
Yes
Yes
PCI Bus Action
Release
Continue driving to ground
Release
As this reset must be performed in conjunction with RSTIN# being asserted, the PCI busses
behave as described in Section 4.8.2.2. However, since the bus is driven to ground until the hot
plug mode is determined (hot plug either does not exist or exists but not in single-slot mode), the
bus must first be put in a state where it looks IDLE.
Intel^® 82870P2 P64H2 Datasheet
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