82870P2P64H2 Datasheet, PDF (119/217 Pages) –

Functional Description
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4.1.8
4.1.9
Lock Cycles
A lock is established when a memory read from the hub interface that targets PCI with the lock bit
set, and at least one byte enable active, is responded to with a PxTRDY# by a PCI target. The
P64H2 does not support a split-lock request when no byte enables are asserted on the initial locked
read request. The bus is unlocked when the Unlock Special Cycle is sent on the hub interface.
When the bus is locked, if a memory cycle originates on PCI that is outside the range of the
memory windows, the cycle is retried. No I/O cycles that are destined across the bridge are
accepted, whether the bus is locked or not, and will master abort.
Once the bus is locked, any hub interface cycle to PCI will be driven with the PxLOCK# pin, even
if that particular cycle is not locked. This should not occur; this is because under lock, peer-to-peer
accesses should be blocked.
When one PCI bus segment is locked, the other is still free to accept cycles (i.e., that bus is not
locked). However, these cycles must not be allowed to proceed on the hub interface or the locked
PCI segment. Therefore, once the PCI bus is locked, no more cycles must proceed onto the hub
interface from the non-locked PCI segment, or from the I/OxAPICs.
Error Handling
The P64H2 checks and generates ECC or parity on the hub interface and parity on the PCI
interfaces. Parity errors must always be reported to some system level software, typically the
device driver or the OS. This section describes how a standard PCI bridge handles these errors.
For enhanced error detection, see Section 4.9.
To support error reporting on the PCI bus, the P64H2 implements the following:
• PxPERR# and PxSERR# signals on PCI
• DO_SERR special cycle on the hub interface
• Primary Device Status Register (PD_STS Register, offset 06–07h) and Secondary Status
Register (SECSTS Register, offset 1E–1Fh)
The P64H2 does not have the PERR# or SERR# pins on the hub interface. Further, the P64H2 is
not capable of generating NMI, SMI, or INTR. If enabled, the P64H2 reports the error using the
hub interface DO_SERR special cycle. The device receiving this cycle must forward that cycle to
a device that can generate the error condition (NMI, SMI, SCI) to the processor.
Intel^® 82870P2 P64H2 Datasheet
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