82870P2P64H2 Datasheet, PDF (61/217 Pages) –

Register Description
R
3.2.36
RAS_PDH—RAS PCI Data High 32 bits Register
(D29,31: F0)
Offset:
7C–7Fh
Default Value: xxxxxxxxh
Attribute:
Size:
RO
32 bits
This register contains the upper 32 bits of PCI data.
Bits
Description
31:0
PCI Data – High 32 bits (DTA). This field is only valid if the AEP, DEP, PRTA, PRMA, or DEBO
bits are set in the RAS_STS Register (60h).
3.2.37
RAS_HH—RAS Hub Interface Header Register (D29,31: F0)
Offset:
80–83h
Default Value: xxxxxxxxh
Attribute:
Size:
RO
32 bits
This register contains information from the first 32 bits of the hub interface header packet. This
represents the entire header as seen on the hub interface – including reserved bits. This field is
only visible from device 31.
Bits
Description
Header (HDR). This field contains the 32-bit header of the hub interface packet. It is only valid if
31:0 the AEHM, AEHS, DEHM, DEHS, DEBI, HTA, or HMA bits are set in the RAS_STS Register
(60h).
3.2.38
RAS_HAL—RAS Hub Interface Address Low 32 Bits
Register (D29,31: F0)
Offset:
84–87h
Default Value: xxxxxxxxh
Attribute:
Size:
RO
32 bits
This register contains information related to the low 32-bits of the hub interface packet address.
This represents the entire address as seen on the hub interface – including bits [1:0].
Bits
Description
Low 32-bits of Address (ADR). This field is only visible from device 31. The field contains the
low 32-bits of the address from the hub interface packet. On read completion packets, where no
31:0 address is sent on the hub interface, the address from the perceived destination (based upon the
Hub ID / Pipe ID) is used. This field is only valid if the AEHM, AEHS, DEHM, DEHS, HTA, or
HMA bits are set in the RAS_STS Register (60h).
Intel^® 82870P2 P64H2 Datasheet
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