82870P2P64H2 Datasheet, PDF (15/217 Pages) –

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Intel^® 82870P2 P64H2 Features
ƒ Primary bus (the Hub Interface)
ƒ Hot Plug Controller
 16 bit data interface
 1 interface per PCI bus segment
 8x clock modes
 Parallel support for 1 and 2 slot systems,
 64-bit and 32-bit addressing support
updates for PCI-X support.
 Parity/ECC Support
 66 MHz base clock
ƒ Buffer Architecture (per interface)
 4 KB of data, split into four 1024-byte
 Parallel Termination
buffers, for inbound read requests from
ƒ Secondary bus (2 PCI Bus Interfaces)
PCI / PCI-X agents.
 PCI Specification, Revision 2.2 compliant
 1.5 KB for inbound write transactions.
 PCI-PCI Bridge Specification, Revision 1.1 ^{ 128 bytes for outbound read completions}
compliant
 16 outbound commands for completions and
 PCI-X Specification, Revision 1.0 compliant
requests.
 66 MHz 64bit, 3.3 V PCI bus (5 V Tolerant) ^{ 16 inbound commands (posted and non-}
 6 REQ/GNT per PCI bus segment (Internal
posted)
arbiter only)
ƒ I/O APIC
 Decoupled operation from Hub interface
 1 interface per PCI bus segment
 64 bit addressing for inbound and outbound ^{ Supports up to 24 interrupts (16 pins) per}
transactions
interface
 Supports outbound LOCK# cycles
 Serial interface for future PCG product
 Fast Back-to-Back capable Bus parking on
 Compatible with both IA-32 and IA-64
Hub Interface
 Boot interrupt output
 Bus parking on last PCI agent
ƒ Test/Debug
 Up to 4 active and 4 pending inbound
 Pilot Mode to monitor internals
delayed transactions, and 1 outbound
 Head-to-Head Mode to test two P64H2s tied
delayed transaction per interface
together with no MCH
 Fair arbitration algorithm between each PCI
interface for ownership of Hub Interface
based upon the maximum bandwidth
requirements on each interface
 PCI Bus B (with APIC B and Hot Plug
ƒ Other features
 Peer-to-peer memory writes between PCI
segments with fence ordering
 Trapping of address / command for first
cycle with parity/ECC errors.
Controller B) can be hidden for a product
sku via a fuse
 Parity protection of SRAM data
ƒ SMBus Interface
 Full read/write access to all Configuration
and Memory registers
 No accesses to PCI bus or Hub Interface
Intel^® 82870P2 P64H2 Datasheet
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