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82870P2P64H2 Datasheet, PDF (26/217 Pages) –
Signal Description
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Table 5. PCI Bus Interface 64-bit Extension Interface B Signals
Signal
PBAD[63:32]
PBC/BE[7:4]#
PBPAR64
PBREQ64#
PBACK64#
Type
Description
PCI Address/Data: These signals are a multiplexed address and data bus. This
bus provides an additional 32 bits to the PCI bus. During the data phases of a
transaction, the initiator drives the upper 32 bits of 64-bit write data, or the target
drives the upper 32 bits of 64-bit read data, when PBREQ64# and PBACK64#
I/O are both asserted.
When not driven, PBAD[63:00] are pulled up to a valid logic level through
external resistors. In a 5 V environment use a 2.7 kΩ resistor; in a 3.3 V
environment use a 8.2 kΩ resistor
Bus Command and Byte Enables (Upper 4 bits): These signals are a
multiplexed command field and byte enable field. For both read and write
transactions, the initiator will drive byte enables for the PBAD[63:32] data bits
on PAC/BE[7:4]# during the data phases when PBREQ64# and PBACK64# are
I/O both asserted.
When not driven, PAC/BE[7:4]# are pulled up to a valid logic level through
external resistors. In a 5 V environment use a 2.7 kΩ resistor; in a 3.3 V
environment use a 8.2 kΩ resistor
PCI Interface Upper 32-bits Parity: This signal carries the even parity of the
I/O
36 bits of PBAD[63:32] and PBC/BE[7:4]# for both address and data phases.
When not driven, PBPAR64 is pulled up to a valid logic level through external
resistors.
PCI interface request 64-bit Transfer: This signal is asserted by the initiator to
I/O
indicate that the initiator is requesting a 64-bit data transfer. It has the same
timing as PBFRAME#. When the Intel® P64H2 is the initiator, this signal is an
output. When the P64H2 is the target, this signal is an input.
PCI interface acknowledge 64-bit Transfer: This signal is asserted by the
I/O target only when PBREQ64# is asserted by the initiator. It indicates the target’s
ability to transfer data using 64 bits. It has the same timing as PBDEVSEL#.
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Intel® 82870P2 P64H2 Datasheet