82870P2P64H2 Datasheet, PDF (21/217 Pages) –

Signal Description
R
2.1
Hub Interface
Table 1. Hub Interface
Signal
CLK66
CLK200/CLK200#
HI_[21:0]
PSTRBF
PSTRBS
PUSTRBF
PUSTRBS
HI_RCOMP
HI_VREF
HI_VSWING
Type
Description
I Hub Interface Clock In: This is a 66 MHz clock input.
I
200 MHz Differential Clock Input: This clock pair is a 200 MHz clock
input.
I/O Hub Interface Signals:
I/O
Hub Interface Strobe: One of two differential strobe signal pairs used to
transmit and receive lower data packet over the hub interface.
I/O
Hub Interface Strobe Complement: One of two differential strobe signal
pairs used to transmit and receive lower data packet over the hub interface.
I/O
Hub Interface Upper Strobe: One of two differential strobe signal pairs
used to transmit and receive upper data packet over the hub interface.
Hub Interface Upper Strobe Complement: One of two differential strobe
I/O signal pairs used to transmit and receive upper data packet over the hub
interface.
I/O Hub Interface Compensation: Used for I/O buffer compensation.
I Hub Interface Reference Voltage: See Section 2.8.
I Hub Interface Reference Swing Voltage: See Section 2.8.
Table 2. PCI Bus Interface A Signals
Signal
PAAD[31:0]
PAC/BE[3:0]#
PAPAR
PADEVSEL#
PAFRAME#
Type
Description
PCI Address/Data: These signals are a multiplexed address and data bus.
I/O
During the address phase or phases of a transaction, the initiator drives a
physical address on PAAD[31:0]. During the data phases of a transaction, the
initiator drives write data, or the target drives read data.
Bus Command and Byte Enables: These signals are a multiplexed command
field and byte enable field. During the address phase or phases of a transaction,
I/O the initiator drives the transaction type on PAC/BE[3:0]#. For both read and
write transactions, the initiator drives byte enables on PAC/BE[3:0]# during the
data phases.
Parity: Even parity calculated on 36 bits (PAAD[31:0] plus PAC/BE[3:0]#). It is
I/O
calculated on all 36 bits, regardless of the valid byte enables. It is driven
identically to the PAAD[31:0] lines, except it is delayed by exactly one PCI
clock.
Device Select: The Intel® P64H2 asserts PADEVSEL# to claim a PCI
transaction. As a target, the P64H2 asserts PADEVSEL# when a PCI master
peripheral attempts an access to an internal address or an address destined for
I/O the hub interface. As an initiator, PADEVSEL# indicates the response to a
P64H2-initiated transaction on the PCI bus. PADEVSEL# is tri-stated from the
leading edge of PCIRST#. PADEVSEL# remains tri-stated by the P64H2 until
driven as a target.
Frame: FRAME# is driven by the Initiator to indicate the beginning and duration
I/O of an access. While PAFRAME# is asserted, data transfers continue. When
FRAME# is negated, the transaction is in the final data phase.
Intel^® 82870P2 P64H2 Datasheet
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