82870P2P64H2 Datasheet, PDF (151/217 Pages) –

Functional Description
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4.3.3.2
4.3.3.3
4.3.4
4.3.5
In hot plug terms, this is the equivalent of the “BUSEN#” signal.
• After a final variable period of time, the card is taken out of reset. When this occurs, the slot
reset pin (HxRESETA#) will be continuously driven high. In hot plug terms, this is the
equivalent of the “PCIRST#” signal to the PCI-X card.
Note that when the controller is operating in single slot mode, there is no provision to run in CBL
(connect bus last) mode. The controller must be programmed to run in connect bus first mode
(CBF mode).
Aborting Outbound PCI Cycles When Card is Disconnected
When a PCI-X card is not present in a multi-slot system, it has been isolated. This means that all
cycles destined for that particular card (peer traffic or other processor-based traffic) will master
abort on the PCI bus because no PxDEVSEL# will be driven. To be consistent in a single-slot
system, the P64H2 must master abort cycles that are destined for that PCI bus when the card is
disconnected.
Therefore, the PCI interface / buffer interface will have to internally master abort all outbound
transactions destined for that PCI bus until the PCI-X card has been fully powered up, connected
to the bus and out of reset. This will be seen as a primary bus master abort in the system, and this
will not be reflected in the Received Master Abort (RMA) bit in the bridge configuration registers.
Special Note on M66EN in Single Slot Mode
In single slot mode, the P64H2 never drives the PxM66EN pin. This is because there is no
isolation logic on PxM66EN, and if the P64H2 drove PxM66EN to ground to indicate the bus was
operating in 33 MHz mode, it could not sample the PxM66EN capabilities from the card to
determine whether the card was 66 MHz capable.
Generating SCI Instead of Interrupt
If the hot plug controller is programmed to generate an SCI instead of an interrupt by setting bit 14
of the ABAR Register, all sources of interrupt will be instead routed to a new SCI pin. This pin is
multiplexed onto PAIRQ7. All logic functions the same as for interrupts – if the interrupt source is
masked, no SCI is generated.
Disabling the Hot Plug Controller
If the HPx_SLOT[2:0] pins are strapped to 000 or 111 when PWROK goes high, the hot plug
controller will be disabled. In this mode, all hot plug output pins (serial mode pins) are driven to 0.
Also, the hot plug controller will not accept configuration or memory read/write transactions. The
controller will essentially "disappear" from the system.
Intel^® 82870P2 P64H2 Datasheet
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