82870P2P64H2 Datasheet, PDF (34/217 Pages) –

Register Description
R
3 Register Description
The Intel® P64H2 contains registers for its hub interface to PCI bridges, hot plug controller,
IOAPIC controller, and SMBus interface. This chapter describes these registers. A detailed bit
description is provided. For register access description, refer to Section 4.4.
PCI Configuration Registers
The P64H2 contains three PCI Devices that reside in Function 0—Hub Interface-to-PCI Bridge
(Device 31 and 29), I/O APIC devices (Device 28 and 30), and the hot plug controller
(Device 31).
• Hub Interface-to-PCI Bridge (D31, 29: F0). This portion of the P64H2 implements the
buffering and control logic between PCI and the hub interface. The PCI bus arbitration is
handled by these PCI devices. The PCI decoder in this device must decode the ranges for hub
interface to the MCH. This register set also provides support for Reliability, Availability, and
Serviceability (RAS). Device 31 is intended for the Hub Interface to PCI A Bridge and device
29 is intended for Hub Interface to PCI B Bridge.
• I/OxAPIC Devices (D28, 30: F0). The P64H2 implements a variation of the APIC known as
the I/OxAPIC. There are two I/OxAPIC devices on the P64H2 and they reside on the primary
bus. Device 28 is intended to be used with interrupts from PCI Bus A and Device 30 is
intended to be used with interrupts on PCI Bus B.
• Hot Plug Controller (Device 31: F0). There are two hot plug controllers; one for PCI Bus A
and one for PCI Bus B. These controllers reside on the secondary PCI bus.
The P64H2 supports PCI configuration space accesses using the mechanism denoted as
Configuration Mechanism #1 in the PCI specification. Refer to Section 4.1.6 for information on
accessing the P64H2 PCI configuration registers.
Memory-Mapped Registers
• I/OxAPIC. In addition to the PCI Configuration Registers mentioned above, the I/OxAPIC
memory-mapped registers are located in the processor memory space located by the MBAR
Register (PCI offset 10h) and MBARU Register (PCI offset 14h). MBAR and MBARU are
located in the I/OxAPIC PCI Configuration space.
• Hot Plug Controller. In addition to the PCI Configuration Registers mentioned above, the
hot plug controller memory-mapped registers are located in the processor memory space
located by the MBAR Register (PCI offset 10h). MBAR is located in the hot plug controller
PCI Configuration space.
SMBus Port Registers
• SMBus interface. The SMBus does not have any PCI configuration registers. These registers
are only accessible via the SMBus port (see Section 3.5).
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Intel^® 82870P2 P64H2 Datasheet