82870P2P64H2 Datasheet, PDF (154/217 Pages) –

Functional Description
R
natural alignment to a 1 MB boundary. The low 20 bits of the limit address are assumed to be all
1s, which results in an alignment to the top of a 1 MB block.
The upper 32-bits of the range are defined by a 32-bit base register at offset 28h in configuration
space, and a 32-bit limit register at offset 2Ch.
Note: Setting the entire base (with upper 32-bits) to a value greater than that of the limit turns off the
memory range.
4.4.3 VGA Addressing
When a VGA-compatible device exists behind a P64H2 bridge, the VGA Enable bit (bit 3) in the
Bridge Control Register must be set (offset 3E–3Fh). If this bit is set, the P64H2 forwards all
transactions addressing the VGA frame buffer memory and VGA I/O registers from the hub
interface to PCI, regardless of the values of the P64H2 base and limit address registers. The
P64H2 will not forward VGA frame buffer memory accesses to the hub interface regardless of the
values of the memory address ranges. However, the I/O Enable and Memory Enable bits in the
PD_CMD Register must still be set. When the bit is cleared, the P64H2 forwards transactions
addressing the VGA frame buffer memory and VGA I/O registers from the hub interface to PCI if
the defined memory address ranges enable forwarding. All accesses to the VGA frame buffer
memory are forwarded from PCI to the hub interface if the defined memory address ranges enable
forwarding. However, the master enable bit must still be set. The VGA I/O addresses are never
forwarded to the hub interface.
The VGA frame buffer consists of the following memory address range:
000A_0000h–00B_FFFFh
The VGA I/O addresses consist of the I/O addresses 3B0h–3BBh and 3C0h–3DFh. These I/O
addresses are aliased every 1 KB throughout the first 64 KB of I/O space. This means that address
bits [9:0] (3B0h–3BBh and 3C0h–3DFh) are decoded, [15:10] are not decoded and can be any
value, and address bits [31:16] must be all 0s.
Note: If software sets the VGA enable bit in one bridge, the ISA enable bit must be set in the other
bridge.
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Intel^® 82870P2 P64H2 Datasheet